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    • 71. 发明申请
    • MULTI-CHANNEL INTEGRATOR
    • 多通道整合器
    • US20110068848A1
    • 2011-03-24
    • US12563373
    • 2009-09-21
    • Kai-Lan ChuangGuo-Ming LeeYing-Lieh Chen
    • Kai-Lan ChuangGuo-Ming LeeYing-Lieh Chen
    • G06G7/18
    • G06G7/186
    • A multi-channel integrator is provided. The multi-channel integrator includes an integrator and a plurality of channels. Each of the channels includes an input selector and a unit-gain amplifier. The input selector has a common terminal, a first selecting terminal and a second selecting terminal. The input selector selectively electrically connects the common terminal to the first selecting terminal or to the second selecting terminal. The first selecting terminal of the input selector is coupled to an input terminal of the integrator. An input terminal of the unit-gain amplifier is coupled to the second selecting terminal of the input selector.
    • 提供多通道积分器。 多通道积分器包括积分器和多个通道。 每个通道包括输入选择器和单位增益放大器。 输入选择器具有公共端子,第一选择端子和第二选择端子。 输入选择器选择性地将公共端子电连接到第一选择端子或第二选择端子。 输入选择器的第一选择端耦合到积分器的输入端。 单位增益放大器的输入端耦合到输入选择器的第二选择端。
    • 72. 发明申请
    • BUFFERING CIRCUIT WITH REDUCED DYNAMIC POWER CONSUMPTION
    • 减少动态电力消耗电路
    • US20110032240A1
    • 2011-02-10
    • US12536050
    • 2009-08-05
    • Jia-Hui WangChien-Hung TsaiYing-Lieh ChenChin-Tien Chang
    • Jia-Hui WangChien-Hung TsaiYing-Lieh ChenChin-Tien Chang
    • G09G5/00H03F3/16H03L5/00
    • H03F3/3022G09G3/2092G09G2300/0426G09G2330/021G09G2360/18H03F1/0205
    • A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption.
    • 提供了具有降低功耗的缓冲电路。 输出缓冲电路包括第一和第二放大器电路。 第一放大器电路包括耦合在第一电源电压和低于第一电源电压的第二电源电压之间的第一输入级和第一输出级,以及辅助放电单元,被配置为提供从第一输出节点 在第一放大器电路的放电操作期间到第一中间电源电压。 第二放大器电路包括耦合在第一电源电压和第二电源电压之间的第二输入级和第二输出级,以及辅助充电单元,被配置为提供从第二中间电源电压流向第二输出节点的充电电流 在第二放大器电路的充电操作期间。 第一和第二放大器电路可以具有降低的输出电压范围,从而降低总功耗。
    • 73. 发明授权
    • Multi-channel integrator
    • 多通道积分器
    • US07884662B1
    • 2011-02-08
    • US12561861
    • 2009-09-17
    • Kai-Lan ChuangGuo-Ming LeeYing-Lieh Chen
    • Kai-Lan ChuangGuo-Ming LeeYing-Lieh Chen
    • H03K5/00
    • G06G7/186G06F3/0416G06F3/044
    • A multi-channel integrator includes a first switch, a second switch, and a plurality of integration units. First terminals of the first and second switches receive a first reference voltage. Each of the integration units includes an operational amplifier (OP-AMP), a feedback switch, a third switch, a fourth switch, and a feedback capacitor. A second input terminal of the OP-AMP receives a second reference voltage. Two terminals of the feedback switch are respectively coupled to a first input terminal and an output terminal of the OP-AMP. First terminals of the third switch and the fourth switch are respectively coupled to the first input terminal and the output terminal of the OP-AMP. A first terminal of the feedback capacitor is coupled to the second terminals of the first and the third switches. A second terminal of the feedback capacitor is coupled to the second terminals of the second and the fourth switches.
    • 多通道积分器包括第一开关,第二开关和多个积分单元。 第一和第二开关的第一端子接收第一参考电压。 每个集成单元包括运算放大器(OP-AMP),反馈开关,第三开关,第四开关和反馈电容器。 OP-AMP的第二输入端接收第二参考电压。 反馈开关的两个端子分别耦合到OP-AMP的第一输入端子和输出端子。 第三开关和第四开关的第一端分别耦合到OP-AMP的第一输入端和输出端。 反馈电容器的第一端子耦合到第一和第三开关的第二端子。 反馈电容器的第二端子耦合到第二和第四开关的第二端子。
    • 75. 发明授权
    • Signal interface
    • 信号接口
    • US07460603B2
    • 2008-12-02
    • US11168677
    • 2005-06-28
    • Jung-Zone ChenTsung-Yu WuYing-Lieh Chen
    • Jung-Zone ChenTsung-Yu WuYing-Lieh Chen
    • H04B3/00
    • G09G3/3688G09G2310/0297
    • The present invention discloses a signal interface to transmit a data signal to a driving circuit. The signal interface comprises a first circuit, a second circuit and a data bus. The first circuit comprises a first register. The second circuit comprises a selector, a second register, a receiver and a third register. If the data signal is a single-end signal, the first register and the selector receive the data signal. Then, the selector transmits the data signal to the second register. The data bus transmits the signal saved in the first register and the second register to the driving circuit. If the data signal is a serial signal, the selector receives and transmits the data signal to the receiver to have it transferred to a single-end signal. Then, the signal is transmitted to the third register and output via the data bus.
    • 本发明公开了一种将数据信号发送到驱动电路的信号接口。 信号接口包括第一电路,第二电路和数据总线。 第一电路包括第一寄存器。 第二电路包括选择器,第二寄存器,接收器和第三寄存器。 如果数据信号是单端信号,则第一寄存器和选择器接收数据信号。 然后,选择器将数据信号发送到第二寄存器。 数据总线将保存在第一寄存器和第二寄存器中的信号发送到驱动电路。 如果数据信号是串行信号,则选择器接收并发送数据信号给接收机以将其传送到单端信号。 然后,信号被发送到第三寄存器并通过数据总线输出。
    • 76. 发明授权
    • Source driver
    • 源驱动程序
    • US08717349B2
    • 2014-05-06
    • US12549636
    • 2009-08-28
    • Chien-Hung TsaiJia-Hui WangChin-Tien ChangYing-Lieh Chen
    • Chien-Hung TsaiJia-Hui WangChin-Tien ChangYing-Lieh Chen
    • G06F3/038
    • G09G3/3688G09G2320/0223
    • A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module.
    • 本文提供了适于驱动显示面板的源驱动器。 源驱动器包括第一输出缓冲器,检测模块和转换模块。 第一输出缓冲器增强第一像素信号,从而输出第一增强像素信号。 检测模块检测第一增强像素信号的上升时间。 转换模块响应于用于调整第一输出缓冲器的转换速率的上升时间来调整第一输出缓冲器的驱动能力。 因此,源驱动器中的第一个输出缓冲器可以通过由检测模块和转换模块组成的反馈机制来动态和自动地调整第一输出缓冲器的转换速率。
    • 77. 发明申请
    • LEVEL SHIFTER
    • 水平变化
    • US20120194256A1
    • 2012-08-02
    • US13363750
    • 2012-02-01
    • Ying-Lieh Chen
    • Ying-Lieh Chen
    • H03L5/00
    • H03K19/017509H03K3/356165
    • A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal.
    • 公开了电平移位器,并且包括至少四个1型晶体管和至少4个2型晶体管。 几个类型1晶体管的源极电连接到第一电压端子,而几个类型2晶体管的源极连接到第二电压端子。 电平移位器接收输入信号并输出​​具有较高电压的逻辑等效输出信号,其中输出信号的电压在第一电压端子和第二电压端子的电压之间。
    • 78. 发明申请
    • Display Device and Driving Circuit
    • 显示设备和驱动电路
    • US20110157103A1
    • 2011-06-30
    • US12648016
    • 2009-12-28
    • Pen-Hsin ChenYing-Lieh Chen
    • Pen-Hsin ChenYing-Lieh Chen
    • G06F3/038
    • G09G3/3685G09G2300/0408G09G2310/0275
    • A display device is provided, including a panel, source driver chips, a gate driver chip, a printed circuit board and transmission lines. The panel includes light emitting elements and display cells. The display cells are respectively connected to data lines and gate lines. The source driver chips output pixel signals to the data lines. At least one source driver chip includes a timing controller integrated therein for generating timing control signals and the pixel signals according to an image control signal provided by a host. The gate driver chip outputs corresponding scan signals to the gate lines. The transmission lines are routed on the printed circuit board and connect to the source driver chips.
    • 提供一种显示装置,包括面板,源驱动器芯片,栅极驱动器芯片,印刷电路板和传输线。 面板包括发光元件和显示单元。 显示单元分别连接到数据线和栅极线。 源驱动器芯片将像素信号输出到数据线。 至少一个源驱动器芯片包括集成在其中的定时控制器,用于根据主机提供的图像控制信号产生定时控制信号和像素信号。 栅极驱动器芯片将相应的扫描信号输出到栅极线。 传输线在印刷电路板上布线,并连接到源驱动器芯片。
    • 79. 发明申请
    • SOURCE DRIVER AND OPERATION METHOD THEREOF AND FLAT PANEL DISPLAY
    • 源驱动器及其操作方法和平板显示器
    • US20110122122A1
    • 2011-05-26
    • US12623087
    • 2009-11-20
    • Ying-Lieh Chen
    • Ying-Lieh Chen
    • G06F3/038
    • G09G3/3688G09G3/3614G09G2310/0294G09G2310/0297G09G2310/08G09G2320/0233
    • A source driver, an operation method thereof, and a flat panel display using the same are provided. The source driver includes a data channel, a switch and a switch controller. The data channel latches a pixel data according to timing of a line letch signal, and converts the latched pixel data to a driving signal for driving a display panel. The data channel decides a polarity of the driving signal according to a polarity signal. A first end of the switch is coupled to the data channel to receive the driving signal. The switch controller adjusts a pulse width of the line letch signal to obtain a control signal for controlling the switch according to the polarity signal. A pulse width of a first pulse is smaller than that of a second pulse in the control signal after the polarity signal is changed.
    • 提供源驱动器,其操作方法和使用其的平板显示器。 源驱动器包括数据通道,开关和开关控制器。 数据通道根据线路接收信号的定时锁存像素数据,并将锁存的像素数据转换为用于驱动显示面板的驱动信号。 数据通道根据极性信号决定驱动信号的极性。 开关的第一端耦合到数据通道以接收驱动信号。 开关控制器调节线路接收信号的脉冲宽度,以获得根据极性信号控制开关的控制信号。 在极性信号改变之后,第一脉冲的脉冲宽度小于控制信号中的第二脉冲的脉冲宽度。