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71. 发明授权

US06583499B2 Quad flat non-leaded package and leadframe for use in a quad flat non-leaded package 有权
标题翻译：四面扁平无铅封装和引线框架，用于四方扁平无铅封装
公开(公告)号：US06583499B2
公开(公告)日：2003-06-24
申请号：US09861757
申请日：2001-05-21
申请人： Chien-Ping Huang , Tzong-Dar Her
发明人： Chien-Ping Huang , Tzong-Dar Her
IPC分类号： H01L23495
CPC分类号： H01L23/3114 , H01L23/49503 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/85399 , H01L2924/00014 , H01L2924/181 , H05K3/341 , H05K2201/0373 , H05K2201/10689 , H05K2201/10969 , Y02P70/613 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A quad flat non-leaded package comprises: a die pad having a first upper surface and a corresponding first lower surface thereon a plurality of interlacing slots are formed, each of the interlacing slots extending to the edges of the die pad to form a plurality of island-like blocks; a plurality of leads disposed at the periphery of the die pad, wherein each of the leads has respectively a second upper surface and a corresponding second lower surface coplanar to the surface of the island-like blocks; a chip having an active surface and a corresponding back surface adhered onto the first upper surface of the die pad; and a molding compound encapsulating the chip, the second upper surface, the first upper surface and the interlacing slots while exposing the surface of the island-like blocks and the second lower surface of the leads.
摘要翻译：四边形无铅包装包括：形成具有第一上表面和其上的对应的第一下表面的管芯焊盘，其上形成有多个交缠槽，每个交缠槽延伸到管芯焊盘的边缘以形成多个岛状块多个引线设置在管芯焊盘的周边，其中每个引线分别具有与岛状块的表面共面的第二上表面和相应的第二下表面; 芯片，其具有粘附到芯片焊盘的第一上表面上的活性表面和对应的背面; 以及在使岛状块的表面和引线的第二下表面暴露的同时封装芯片，第二上表面，第一上表面和交织槽的模塑料。

72. 发明授权

US06541854B2 Super low profile package with high efficiency of heat dissipation 有权
公开(公告)号：US06541854B2
公开(公告)日：2003-04-01
申请号：US09894884
申请日：2001-06-29
申请人： Chien-Ping Huang , Tzong-Dar Her
发明人： Chien-Ping Huang , Tzong-Dar Her
IPC分类号： H01L2334
CPC分类号： H01L21/568 , H01L23/4334 , H01L23/49816 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/85001 , H01L2924/00014 , H01L2924/01079 , H01L2924/15173 , H01L2924/15311 , H01L2924/1532 , H01L2924/18165 , Y10T29/49146 , Y10T29/49171 , H01L2924/00 , H01L2224/45099
摘要： A super low profile package with high efficiency of heat dissipation comprises the substrate, the heat sink, the die, the wires and the plastic mold. The heat sink adheres to the ground ring by the extending part of the heat sink, and the first surface of the die adheres to the heat sink. In addition, the die is connected to the substrate by the wires, and the plastic mold encapsulates the die, the heat sink and the wires. The chip package according to the invention possesses the small size and high efficiency of heat dissipation; besides, it also decreases the production cost for eliminating the conventional procedures of taping and de-taping.

73. 发明授权

US06507121B2 Array structure of solder balls able to control collapse 有权
公开(公告)号：US06507121B2
公开(公告)日：2003-01-14
申请号：US09756086
申请日：2001-01-08
申请人： Chien-Ping Huang
发明人： Chien-Ping Huang
IPC分类号： H01L2348
CPC分类号： H01L21/4853 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L25/0657 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06517 , H01L2225/06586 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H05K3/3436 , H05K3/3463 , H05K2201/094 , H05K2201/10234 , H05K2201/10477 , H05K2201/10992 , H05K2201/2036 , H05K2203/041 , Y02P70/613 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A solder ball array type package structure is able to control collapse. The package includes a substrate, a carrier, a plurality of dies, a molding compound and a plurality of solder balls. The substrate has at least one active surface. Pads are located on the first surface of the substrate. The carrier has at least an active surface and a back surface opposite the active surface. A plurality of dies are located on the back surface and the active surface of the carrier. The dies arranged on the active surface are electrically connected to the carrier by flip chip technology. A molding compound encapsulates on the back surface of the carrier to cover the dies on the back surface of the carrier. Solder balls having a base material are provided on the active surface of the carrier in array. At least three solder balls coated with the base material having a high melting-temperature core are further provided in the periphery of the array. The carrier is arranged such that the active surface faces the first surface of the substrate to allow each solder ball correspond to the one of the pads, respectively.

74. 发明授权

US06498391B1 Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same 有权
标题翻译：具有未对准芯片布置的双芯片集成电路封装及其制造方法
公开(公告)号：US06498391B1
公开(公告)日：2002-12-24
申请号：US09473308
申请日：1999-12-28
申请人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
发明人： Chien-Ping Huang , Lian-Cherng Chiang , Michael Chang
IPC分类号： H01L23495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/32014 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48639 , H01L2224/48739 , H01L2224/48839 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85439 , H01L2225/06562 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/10161 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A dual-chip integrated circuit package with unaligned chip arrangement and a method of manufacturing such a dual-chip integrated circuit package are provided. The dual-chip integrated circuit package includes a leadframe having a first set of leads and a second set of leads. The dual-chip integrated circuit package is used to pack two integrated circuit chips in an unaligned chip arrangement, in which the first integrated circuit chip is mounted to one side of the inner part of the first set of leads, and the second integrated circuit chip is mounted to the other side of the same in such a manner as to allow the bonding pads on the second integrated circuit chip to be positioned in the spacing formed between the two sets of leads. This unaligned chip arrangement can help facilitate the wire-bonding process for the bonding pads are the second integrated circuit chip. An encapsulant is used for encapsulating the first integrated circuit chip, the second integrated circuit chip, the set of bonding wires, the second set of bonding wires, the inner part of the first set of leads, and the inner part of the second set of leads. The particular structure of the dual-chip integrated circuit package allows no restriction to the relative size between first two integrated circuit chips, thus allowing flexible selection for the combination of the two integrated circuit chips. Moreover, the dual-chip integrated circuit package are help save layout space on the circuit board and offers more functionality and storage capacity.
摘要翻译：提供了具有未对准芯片布置的双芯片集成电路封装以及制造这种双芯片集成电路封装的方法。双芯片集成电路封装包括具有第一组引线和第二组引线的引线框架。双芯片集成电路封装用于以未对准的芯片布置来封装两个集成电路芯片，其中第一集成电路芯片安装在第一组引线的内部的一侧，第二集成电路芯片以这样的方式安装到其另一侧，即允许第二集成电路芯片上的接合焊盘定位在两组引线之间形成的间隔中。这种未对准的芯片布置可以帮助便于焊接工艺的焊盘是第二个集成电路芯片。密封剂用于封装第一集成电路芯片，第二集成电路芯片，一组接合线，第二组接合线，第一组引线的内部和第二组引线的内部领导。双芯片集成电路封装的特定结构不限制前两个集成电路芯片之间的相对尺寸，从而允许灵活地选择两个集成电路芯片的组合。此外，双芯片集成电路封装有助于节省电路板上的布局空间，并提供更多的功能和存储容量。

75. 发明授权

US06437447B1 Dual-sided chip package without a die pad 有权
标题翻译：双面芯片封装，无芯片
公开(公告)号：US06437447B1
公开(公告)日：2002-08-20
申请号：US09697296
申请日：2000-10-27
申请人： Chien-Ping Huang , Chin-Yuan Hung , Chang-Fu Chen , Jenn-Shyh Yu , Jui-Hsiang Hung
发明人： Chien-Ping Huang , Chin-Yuan Hung , Chang-Fu Chen , Jenn-Shyh Yu , Jui-Hsiang Hung
IPC分类号： H01L2348
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/10162 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： In a dual-sided chip package without a die pad according to the invention, a first die can be fixed directly on the lead fingers of a leadframe, a support bar, or bus bars, while a second die is attached to the first die. Without a die pad, the distance between the surfaces of the dies and the plastic surface of the package therefore gets longer. Thus, the invention enables a large decrease in the probability of generating voids in the plastic and there is no need to grind the dies. Besides, it improves the vibration and floating characteristics of the dies in the manufacturing process and thus prevents the exposure of the bonding wires and the shelling off or breaking of the dies. The invention can raise the yield of chip packages.
摘要翻译：在根据本发明的没有芯片焊盘的双面芯片封装中，第一裸片可以直接固定在引线框架，支撑杆或汇流条的引线上，而第二裸片附接到第一裸片。没有管芯焊盘，因此，模具表面与封装的塑料表面之间的距离变长。因此，本发明能够大大降低在塑料中产生空隙的可能性，并且不需要研磨模具。此外，在制造过程中，提高了模具的振动和浮动特性，防止了接合线的暴露和模具脱壳或断裂。本发明可以提高芯片封装的产量。

76. 发明授权

US06396707B1 Ball grid array package 有权
标题翻译：球栅阵列封装
公开(公告)号：US06396707B1
公开(公告)日：2002-05-28
申请号：US09454006
申请日：1999-12-03
申请人： Chien-Ping Huang , Grace Yang
发明人： Chien-Ping Huang , Grace Yang
IPC分类号： H05K702
CPC分类号： H01L23/49816 , H01L2924/0002 , H05K3/3452 , H05K3/3457 , H05K2201/0989 , H01L2924/00
摘要： A ball grid array package comprises a substrate having a first surface and a second surface, a chip, an insulating material, and a solder ball. The surface of the substrate comprises ball pads, conducting traces, and solder masks wherein the conducting traces are disposed in between the adjacent ball pads, and are covered by the solder mask, in addition, a portion of each of the ball pads is also covered by the solder mask. The solder mask includes an opening positioned in the area corresponding to the ball pads wherein the opening exposes a portion of the surface the ball pad and a portion of the side wall of the ball pad. The chip is disposed on the second surface of the substrate, and is sealed and encapsulated by the insulated material. The solder balls are disposed on the first surface of the substrate, and are positioned at the openings of the ball pads. Additionally, the solder balls are electrically connected to a portion of the surface of the ball pads and a portion of the side wall of the ball pads disposed at the ball pad openings.
摘要翻译：球栅阵列封装包括具有第一表面和第二表面的衬底，芯片，绝缘材料和焊球。衬底的表面包括球垫，导电迹线和焊接掩模，其中导电迹线设置在相邻的球垫之间，并被焊接掩模覆盖，此外，每个球垫的一部分也被覆盖通过焊接面罩。焊接掩模包括位于对应于球垫的区域中的开口，其中开口暴露表面的一部分球垫和球垫的侧壁的一部分。芯片设置在基板的第二表面上，并被绝缘材料密封和封装。焊球设置在基板的第一表面上，并且位于球垫的开口处。此外，焊球与电极焊盘表面的一部分电连接，球垫侧壁的一部分设置在球垫开口处。

77. 发明授权

US06350669B1 Method of bonding ball grid array package to circuit board without causing package collapse 有权
标题翻译：将球栅阵列封装焊接到电路板而不会导致封装崩溃的方法
公开(公告)号：US06350669B1
公开(公告)日：2002-02-26
申请号：US09699888
申请日：2000-10-30
申请人： Han-Ping Pu , Chien-Ping Huang
发明人： Han-Ping Pu , Chien-Ping Huang
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L21/4846 , H01L2224/05571 , H01L2224/05573 , H01L2224/11334 , H01L2224/13099 , H01L2224/14505 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H05K3/3463 , H05K2201/094 , H05K2201/10234 , H05K2201/10992 , H05K2203/041 , Y02P70/613 , H01L2224/05599
摘要： A method is proposed for bonding a BGA (Ball Grid Array) package to a circuit board without causing the collapsing of the BGA package against the circuit board. The proposed method is characterized in the use of two groups of solder balls of different reflow collapse degrees, which are arranged in an interspersed manner among each other in the ball grid array. In one embodiment, the first group of solder balls are homogenously made of a solder material of a specific melting point; and the second group of solder balls each include an outer portion and a core portion, with the outer portion having substantially the same melting point as the first group of solder balls, and the core portion being greater in melting point than the outer portion. In another embodiment, the second group of solder balls are greater in melting point than the first group of solder balls. During the solder-reflow process, when the first group of solder balls are entirely melted, the second group of solder balls are only partly melted or entirely unmelted and thus are capable of providing a solid support to the BGA package to prevent the collapsing of BGA package against circuit board.
摘要翻译：提出了一种用于将BGA（球栅阵列）封装结合到电路板而不引起BGA封装相对于电路板折叠的方法。所提出的方法的特征在于使用不同回流塌陷度的两组焊球，其在球栅阵列中以散布的方式相互排列。在一个实施例中，第一组焊球由具有特定熔点的焊料均质地制成; 并且第二组焊球各自包括外部部分和芯部分，外部部分具有与第一组焊球基本相同的熔点，并且芯部分的熔点大于外部部分。在另一个实施例中，第二组焊球的熔点高于第一组焊球。在焊料回流工艺期间，当第一组焊球完全熔化时，第二组焊球仅部分熔化或完全未熔化，因此能够为BGA封装提供固体支撑以防止BGA的塌陷封装电路板。

78. 发明授权

US06290481B1 Flash-free mold structure for integrated circuit package 失效
标题翻译：无闪存模块结构用于集成电路封装
公开(公告)号：US06290481B1
公开(公告)日：2001-09-18
申请号：US09574878
申请日：2000-05-19
申请人： Chien-Ping Huang
发明人： Chien-Ping Huang
IPC分类号： B29C4514
CPC分类号： B29C45/2701 , H01L21/565 , H01L2924/0002 , H01L2924/00
摘要： A flash-free mold structure is designed for use in the molding of an encapsulant for encapsulating a semiconductor die. The flash-free mold structure includes a first molding piece and a second molding piece. The second molding piece is formed with a resin passage for an encapsulating material to flow therethrough during molding process. It is a characteristic feature of this flash-free mold structure that a cutaway portion, which can be either an one-step cutaway portion or a multi-step cutaway portion, is formed at the rim of the resin passage. The cutaway portion is dimensioned significantly smaller than the resin passage for the retarding the flow speed of the encapsulating material from the resin passage into the cutaway portion during the molding process, thereby preventing the encapsulating material from entering the fissure in the junction between the first and second molding pieces. The resin passage can be either a cull, a runner, or a subrunner defined by the first and second molding pieces. With this flash-free mold structure, the IC packaging quality can be assured and fabrication tools can be prevented from contamination.
摘要翻译：无闪光模具结构被设计用于模制用于封装半导体管芯的密封剂。无闪光模具结构包括第一成型件和第二成型件。第二成型件在模制过程中由用于密封材料的树脂通道形成为流过其中。这种无闪光模具结构的特征在于，在树脂通道的边缘处形成有可以是一步切口部分或多段切口部分的切口部分。切割部分的尺寸明显小于树脂通道，用于在模制过程中阻止封装材料从树脂通道进入切除部分的流动速度，从而防止封装材料在第一和第二部分之间的接合处进入裂缝第二个成型件。树脂通道可以是由第一和第二成型件限定的剔除，流道或辅助材料。利用这种无闪光模具结构，可以确保IC封装质量，并可防止制造工具的污染。

79. 发明授权

US08963298B2 EMI shielding package structure and method for fabricating the same 有权
标题翻译： EMI屏蔽封装结构及其制造方法
公开(公告)号：US08963298B2
公开(公告)日：2015-02-24
申请号：US12769053
申请日：2010-04-28
申请人： Chin-Tsai Yao , Chien-Ping Huang , Chun-Chi Ke
发明人： Chin-Tsai Yao , Chien-Ping Huang , Chun-Chi Ke
IPC分类号： H01L23/552 , H01L23/00
CPC分类号： H01L23/552 , H01L21/561 , H01L21/78 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L24/96 , H01L24/97 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/0105 , H01L2924/01079 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2224/81 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.
摘要翻译： EMI屏蔽封装结构包括具有第一表面和芯片安装区域的基板单元和与第一表面相对的第二表面，形成在第一表面上的金属柱，安装在芯片安装区域上并与之电连接的芯片，在将所述金属柱的一部分从所述密封剂暴露出来的同时覆盖所述芯片和所述第一表面的密封剂以及封装所述密封剂并电连接到所述金属柱的屏蔽膜。进一步提供通过两个切割工艺的上述结构的制造方法。第一切割工艺通过切割密封剂形成凹槽。在凹槽中形成屏蔽膜并与金属柱电连接之后，通过第二切割工艺形成完整的封装结构，从而在克服现有技术中遇到的屏蔽膜的不良接地的同时简化制造工艺。

80. 发明授权

US08653661B2 Package having MEMS element and fabrication method thereof 有权
标题翻译：具有MEMS元件的封装及其制造方法
公开(公告)号：US08653661B2
公开(公告)日：2014-02-18
申请号：US13170424
申请日：2011-06-28
申请人： Chang-Yueh Chan , Chien-Ping Huang , Chun-Chi Ke , Shih-Kuang Chiu
发明人： Chang-Yueh Chan , Chien-Ping Huang , Chun-Chi Ke , Shih-Kuang Chiu
IPC分类号： H01L21/56
CPC分类号： B81C1/00301 , B81B2207/096 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization.
摘要翻译：提供了具有MEMS元件的封装结构，其包括：形成有开口的保护层; 导体分别形成在开口中; 形成在保护层和导体上的导电焊盘; 设置在导电焊盘上的MEMS芯片; 以及形成在用于封装MEMS芯片的保护层上的密封剂。通过将MEMS芯片直接设置在保护层上，以免对不希望地增加厚度的载体（例如晶片或电路板）的需要，本发明减小了封装的整体厚度从而实现小型化。

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