专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US6133097A Method for forming mirror image split gate flash memory devices by forming a central source line slot 有权
标题翻译：通过形成中心源线槽来形成镜像分离门闪存器件的方法
公开(公告)号：US6133097A
公开(公告)日：2000-10-17
申请号：US133969
申请日：1998-08-14
申请人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.
摘要翻译：形成分离栅电极MOSFET器件的方法包括以下步骤。在半导体衬底上形成隧道氧化层。在隧道氧化物层上形成浮栅电极层。在浮栅电极层上形成掩蔽帽。掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。栅电极中心的图案源极线槽向下堆叠到衬底。在源线插槽的底部形成源区。在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。形成自对准漏极区。

72. 发明授权

US6078076A Vertical channels in split-gate flash memory cell 有权
标题翻译：分闸式闪存单元中的垂直通道
公开(公告)号：US6078076A
公开(公告)日：2000-06-20
申请号：US317645
申请日：1999-05-24
申请人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
发明人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.
摘要翻译：通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。衬底中的源极/漏极区域与浮栅电极层自对准。通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图在其中形成控制栅极孔。在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

73. 发明授权

US06803625B2 Method with trench source to increase the coupling of source to floating gate in split gate flash 有权
公开(公告)号：US06803625B2
公开(公告)日：2004-10-12
申请号：US10627013
申请日：2003-07-25
申请人： Chia-Ta Hsieh , Di Son Kuo , Chrong-Jun Lin , Wen-Ting Chu
发明人： Chia-Ta Hsieh , Di Son Kuo , Chrong-Jun Lin , Wen-Ting Chu
IPC分类号： H01L2978
CPC分类号： H01L27/11521 , H01L27/115
摘要： A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

74. 发明授权

US5970341A Method for forming vertical channels in split-gate flash memory cell 失效
标题翻译：分闸式闪存单元形成垂直通道的方法
公开(公告)号：US5970341A
公开(公告)日：1999-10-19
申请号：US988772
申请日：1997-12-11
申请人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
发明人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole. Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.
摘要翻译：通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。衬底中的源极/漏极区域与浮栅电极层自对准。通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图。在其中形成控制门孔。在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

75. 发明授权

US06624025B2 Method with trench source to increase the coupling of source to floating gate in split gate flash 有权
标题翻译：具有沟槽源的方法，以增加源在分流栅闪存中的浮动栅极的耦合
公开(公告)号：US06624025B2
公开(公告)日：2003-09-23
申请号：US09940158
申请日：2001-08-27
申请人： Chia-Ta Hsieh , Di Son Kuo , Chrong-Jun Lin , Wen-Ting Chu
发明人： Chia-Ta Hsieh , Di Son Kuo , Chrong-Jun Lin , Wen-Ting Chu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.
摘要翻译：提供了具有倾斜沟槽源的改进的编程和擦除速度的分裂栅极闪存单元，以及其形成方法。这通过形成两个浮动栅极和它们各自的控制栅极共享公共源极区域来实现。在源区域中形成沟槽，并且壁倾斜以具有倾斜。以倾斜角进行源植入，并且沟槽衬有栅极氧化物层。随后，进行源植入物的横向扩散，然后进行热循环。发现扩散源的横向放大基本上增加了分裂栅极闪存单元的耦合比。

76. 发明授权

US06544828B1 Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM 有权
标题翻译：在隔离边缘添加多芯片，以提高EEPROM上高压NMOS的耐用性
公开(公告)号：US06544828B1
公开(公告)日：2003-04-08
申请号：US10044860
申请日：2001-11-07
申请人： Wen-Ting Chu , Di-Son Kuo , Jack Yeh , Chia-Ta Hsieh , Chrong-Jung Lin , Sheng-Wei Tsaur
发明人： Wen-Ting Chu , Di-Son Kuo , Jack Yeh , Chia-Ta Hsieh , Chrong-Jung Lin , Sheng-Wei Tsaur
IPC分类号： H01L218234
CPC分类号： H01L29/402 , H01L21/28123 , H01L21/823481 , H01L29/4238
摘要： A method for improving the endurance and robustness of high voltage NMOS devices by forming a conductive field plate at the edge of a shallow trench isolation region at the drain side only is described. Active areas are separated by isolation regions in a substrate. A gate oxide layer is grown on the active areas. A conducting layer is deposited overlying the gate oxide layer and patterned to form gate electrodes in the active areas and to form conductive strips overlapping both the active areas and the isolation areas at an isolation's edge on a drain side of the active areas wherein the conductive strips reduce the electric field at the isolation's edge in the fabrication of an integrated circuit device.
摘要翻译：描述了通过在漏极侧的浅沟槽隔离区域的边缘处形成导电场板来提高高电压NMOS器件的耐久性和鲁棒性的方法。活性区域通过衬底中的隔离区域分离。在活性区域上生长栅极氧化物层。导电层沉积在栅极氧化物层上并被图案化以在有源区域中形成栅电极，并且在有源区域的漏极侧上的隔离边缘处形成与有源区域和隔离区域重叠的导电条带，其中导电条在集成电路器件的制造中减小隔离边缘的电场。

77. 发明授权

US06420233B1 Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate electrode dopant profile 有权
标题翻译：采用非线性多晶硅浮栅电极掺杂剂分布的分流栅场效应晶体管（FET）器件
公开(公告)号：US06420233B1
公开(公告)日：2002-07-16
申请号：US09766860
申请日：2001-01-19
申请人： Chia-Ta Hsieh , Di-Son Kuo , Jake Yeh , Chung-Li Chang , Wen-Ting Chu , Chrong-Jung Lin
发明人： Chia-Ta Hsieh , Di-Son Kuo , Jake Yeh , Chung-Li Chang , Wen-Ting Chu , Chrong-Jung Lin
IPC分类号： H01L29336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is employed a doped polysilicon floating gate electrode having an central annular portion having a higher dopant concentration than a peripheral annular portion of the doped polysilicon floating gate electrode. The higher dopant concentration within the central annular portion of the doped polysilicon floating gate electrode provides enhanced programming speed properties of the split gate field effect transistor (FET) device. The lower dopant concentration within the peripheral annular portion of the doped polysilicon floating gate electrode provides enhanced erasing speed properties within the split gate field effect transistor (FET) device under certain circumstances of fabrication of the split gate field effect transistor (FET) device.
摘要翻译：在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，采用掺杂多晶硅浮栅，其具有中间环状部分，其掺杂浓度高于周边环形掺杂多晶硅浮栅电极的一部分。掺杂多晶硅浮置栅电极的中心环形部分内的较高掺杂剂浓度提供了分裂栅极场效应晶体管（FET）器件的增强的编程速度特性。在掺杂多晶硅浮置栅电极的外围环形部分内的较低掺杂剂浓度在分裂栅极场效应晶体管（FET）器件的制造的某些情况下在分裂栅极场效应晶体管（FET）器件内提供增强的擦除速度特性。

78. 发明授权

US06326662B1 Split gate flash memory device with source line 有权
标题翻译：分流闸闪存器件与源极线
公开(公告)号：US06326662B1
公开(公告)日：2001-12-04
申请号：US09633643
申请日：2000-08-07
申请人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.
摘要翻译：形成分离栅电极MOSFET器件的方法包括以下步骤。在半导体衬底上形成隧道氧化层。在隧道氧化物层上形成浮栅电极层。在浮栅电极层上形成掩蔽帽。掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。栅电极中心的图案源极线槽向下堆叠到衬底。在源线插槽的底部形成源区。在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。形成自对准漏极区。

79. 发明授权

US06297099B1 Method to free control tunneling oxide thickness on poly tip of flash 有权
标题翻译：自由控制闪光多头尖端的隧道氧化物厚度的方法
公开(公告)号：US06297099B1
公开(公告)日：2001-10-02
申请号：US09765045
申请日：2001-01-19
申请人： Chia-Ta Hsieh , Di-Son Kuo , Jack Yeh , Chrong Jung Lin , Wen-Ting Chu , Chung-Li Chang
发明人： Chia-Ta Hsieh , Di-Son Kuo , Jack Yeh , Chrong Jung Lin , Wen-Ting Chu , Chung-Li Chang
IPC分类号： H01L218247
CPC分类号： H01L21/28273 , H01L29/42324 , Y10S438/981
摘要： A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.
摘要翻译：一种制造浮栅/字线装置的方法，包括以下步骤。提供半导体结构。在半导体结构上方形成浮栅部分。浮动门部分具有侧壁和顶面。多晶氧化物部分形成在浮动栅极的顶表面上。在半导体结构，多晶氧化物部分和多晶氧化物部分之上形成多层氧化物层。所述多晶硅氧化物层具有初始厚度，并且包括：与所述浮动栅极部分相邻的所述半导体结构的至少一部分上的字线区域部分; 浮动部分侧壁上的侧壁区域部分; 以及多个氧化物部分上方的顶部。互折层氧化物层的顶部的初始厚度减小到第二厚度，而不会减小多晶氧化物字线区域部分的初始厚度或多余氧化物侧壁区域部分的明显部分。在多晶硅层上形成多晶硅层。将结构图案化以形成浮动栅/字线装置。

80. 发明授权

US06468863B2 Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof 有权
标题翻译：采用电介质阻挡层的分流栅场效应晶体管（FET）器件及其制造方法
公开(公告)号：US06468863B2
公开(公告)日：2002-10-22
申请号：US09761276
申请日：2001-01-16
申请人： Chia-Ta Hsieh , Di-Son Kuo , Jake Yeh , Chuan-Li Chang , Wen-Ting Chu , Sheng-Wei Tsaur
发明人： Chia-Ta Hsieh , Di-Son Kuo , Jake Yeh , Chuan-Li Chang , Wen-Ting Chu , Sheng-Wei Tsaur
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.
摘要翻译：在制造分裂栅极场效应晶体管的方法和使用该方法制造的分裂栅极场效应晶体管的两者中，采用形成为覆盖浮置栅极的第一部分和半导体的第一部分的图案化氮化硅阻挡介电层衬底邻近浮动栅极的第一部分。在半导体衬底的第一部分内，当制造分裂栅极场效应晶体管时，最终形成源极/漏极区域，尤其是源极区域。图案化的氮化硅阻挡介电层在制造分离栅场效应晶体管离子注入损坏浮栅和浮栅电极边缘的氧化损失时禁止。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式