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    • 72. 发明申请
    • Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules
    • 命令排队智能存储传输管理器,用于将数据传送到原始NAND闪存模块
    • US20110213921A1
    • 2011-09-01
    • US13104257
    • 2011-05-10
    • Frank YuCharles C. LeeAbraham C. Ma
    • Frank YuCharles C. LeeAbraham C. Ma
    • G06F12/02
    • G06F12/0246G06F3/061G06F3/0659G06F3/0688G06F12/0607G06F2212/7208G11C13/0004
    • A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
    • 闪存模块具有通过NVM控制器通过物理块地址(PBA)总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘(SSD)的系统板上。 NVM控制器将逻辑块地址(LBA)转换为物理块地址(PBA)。 闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平,而在信道内的进一步的交织和重新映射可由NVM控制器执行。 智能存储交换机使用SDRAM缓冲区,在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。 剩余部分指向SDRAM中主机数据的位置。 命令队列存储主机命令的Q,R。
    • 75. 发明申请
    • Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System
    • 用于混合块和页模式闪存系统的混合二级映射表
    • US20090193184A1
    • 2009-07-30
    • US12418550
    • 2009-04-03
    • Frank YuCharles C. LeeAbraham C. MaMyeongjin Shin
    • Frank YuCharles C. LeeAbraham C. MaMyeongjin Shin
    • G06F12/02G06F12/00
    • G06F12/0246G06F2212/7203G06F2212/7208G11C11/5628G11C11/5678G11C13/00G11C13/0004G11C2211/5641
    • A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced.
    • 混合固态盘(SSD)具有多级单元(MLC)或单级单元(SLC)闪存,或两者兼有。 SLC闪存可能由使用较少单元状态的MLC仿真。 NVM控制器将逻辑块地址(LBA)转换为物理块地址(PBA)。 大多数数据被块映射并存储在MLC闪存中,但是一些关键或高频数据被页映射以减少块重定位复制。 混合映射表具有第一级和第二级。 只有第一级用于块映射数据,但是这两个级别都用于页映射数据。 第一级包含一个块页位,指示数据是块映射还是页映射。 第一级表中的PBA字段映射块映射数据,而虚拟字段指向存储页面映射数据的PBA和页码的二级表。 页面映射数据由频率计数器或扇区计数来标识。 SRAM空间减少。