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71. 发明申请

US20050122770A1 Method to reduce switch threshold of soft magnetic films 有权
标题翻译：降低软磁膜开关阈值的方法
公开(公告)号：US20050122770A1
公开(公告)日：2005-06-09
申请号：US11037280
申请日：2005-01-18
申请人： Denny Tang
发明人： Denny Tang
IPC分类号： G11C11/15 , G11C11/00
CPC分类号： G11C11/15
摘要： In magnetic memories it is important to be able to switch the states of the memory elements using minimal power i.e. external fields of minimal intensity. This has been achieved by giving each memory element an easy axis whose direction parallels its minimum surface dimension. Then, when the magnetic state of the element is switched by rotating its direction of magnetization, said rotation is assisted, rather than being opposed, by the crystalline anisotropy. Consequently, relative to the prior art, a lower external field is required to switch the state of the element.
摘要翻译：在磁存储器中，重要的是能够使用最小功率即最小强度的外部场来切换存储元件的状态。这已经通过给每个存储元件一个方向平行于其最小表面尺寸的容易轴来实现。然后，当通过旋转其磁化方向来切换元件的磁状态时，通过晶体各向异性来辅助而不是相反的旋转。因此，相对于现有技术，需要较低的外部场来切换元件的状态。

72. 发明授权

US06778433B1 High programming efficiency MRAM cell structure 有权
标题翻译：高编程效率MRAM单元结构
公开(公告)号：US06778433B1
公开(公告)日：2004-08-17
申请号：US10163845
申请日：2002-06-06
申请人： Denny Tang
发明人： Denny Tang
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： Currently it takes up to 10 mA current in the programming line to switch a cell in an MRAM. This current is high enough to cause electro-migration problems over the life of an array so there is a need for a more efficient way to generate the programming field. The present invention solves this problem by (1) passing the programming current inside the cell, i.e, through the pinned layer, and (2) surrounding each program line with a sheath of high permeability material which covers the wire except for a gap located directly above or below the memory element. This high permeability layer may be a conductor or an insulator, the latter case allowing it to make direct contact with the memory element.
摘要翻译：目前，编程行中需要高达10 mA的电流来切换MRAM中的单元。该电流足够高以致在阵列的寿命期间引起电迁移问题，所以需要一种更有效的方式来产生编程领域。本发明通过以下方式解决了这个问题：（1）将编程电流传递到电池单元内，即通过被钉扎层，以及（2）围绕每个程序线的高导磁率材料护套覆盖电线，除了直接定位的间隙高于或低于存储元件。该高磁导率层可以是导体或绝缘体，后一种情况允许其与存储元件直接接触。

73. 发明授权

US06711053B1 Scaleable high performance magnetic random access memory cell and array 失效
标题翻译：可扩展的高性能磁性随机存取存储单元和阵列
公开(公告)号：US06711053B1
公开(公告)日：2004-03-23
申请号：US10353583
申请日：2003-01-29
申请人： Denny Tang
发明人： Denny Tang
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： An MRAM array has groupings of MRAM cells that are interconnected by word control lines, bit lines, primary program control lines, and secondary program control lines. Each MRAM cell is comprised of a magnetic tunnel junction and a primary switching device connected between the magnetic tunnel junction and one of the primary program control lines to provide the write current through the pinned layer of the magnetic tunnel junction. In a first embodiment, the pinned ferromagnetic layer is connected directly to a segmented local program control line that eliminates parasitic currents during read or write of an MRAM cell. In a second embodiment, the MRAM cell includes a secondary switching device connected between the second side of the ferromagnetic layer the local program control line. The secondary program control lines are segmented to eliminate parasitic currents during a read or write of an MRAM cell.
摘要翻译： MRAM阵列具有通过字控制线，位线，主程序控制线和辅助程序控制线互连的MRAM单元的分组。每个MRAM单元包括磁性隧道结和连接在磁性隧道结与主要程序控制线之一之间的主要开关装置，以提供穿过磁性隧道结的被钉扎层的写入电流。在第一实施例中，钉扎铁磁层直接连接到分段的本地程序控制线，其消除在MRAM单元的读取或写入期间的寄生电流。在第二实施例中，MRAM单元包括连接在铁磁层的第二侧本地程序控制线之间的次级开关装置。次级程序控制线被分段以消除在MRAM单元的读取或写入期间的寄生电流。

74. 发明授权

US08213220B2 Device and method of programming a magnetic memory element 有权
标题翻译：编程磁记忆元件的装置和方法
公开(公告)号：US08213220B2
公开(公告)日：2012-07-03
申请号：US12687608
申请日：2010-01-14
申请人： Yu-Jen Wang , Hsu-Chen Cheng , Denny Tang
发明人： Yu-Jen Wang , Hsu-Chen Cheng , Denny Tang
IPC分类号： G11C11/00
CPC分类号： G11C11/1693 , G11C11/161 , G11C11/1659 , G11C11/1675
摘要： The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction. The first and second currents cause the non-fixed magnetization of the second magnetic element to toggle between substantially parallel to the fixed magnetization of the first magnetic element and between substantially antiparallel to the fixed magnetization of the first magnetic element.
摘要翻译：本公开提供了一种非易失性存储器件。存储器件包括具有固定磁化强度的第一磁性元件。存储器件还包括具有非固定磁化强度的第二磁性元件。存储器件还包括在第一和第二磁性元件之间的阻挡层。单向电流源电耦合到第一和第二磁性元件。当前源被配置为向第一和第二存储器元件提供第一电流。第一电流具有第一电流密度并且处于第一方向。电流源还被配置为向第一和第二磁性元件提供第二电流。第二电流具有与第一电流密度不同的第二电流密度，并且处于第一方向。第一和第二电流导致第二磁性元件的非固定磁化在基本上平行于第一磁性元件的固定磁化之间以及基本上反平行于第一磁性元件的固定磁化之间翻转。

75. 发明授权

US08120947B2 Spin torque transfer MRAM device 有权
标题翻译：旋转扭矩传递MRAM装置
公开(公告)号：US08120947B2
公开(公告)日：2012-02-21
申请号：US12537093
申请日：2009-08-06
申请人： Yu-Jen Wang , Denny Tang , Hsu-Chen Cheng
发明人： Yu-Jen Wang , Denny Tang , Hsu-Chen Cheng
IPC分类号： G11C11/00
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1675
摘要： The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.
摘要翻译：本公开提供了一种磁存储元件。存储元件包括磁隧道结（MTJ）元件和电极。电极包括钉扎层，钉扎层和非磁性导电层。在一个实施例中，MTJ元件包括具有第一表面区域的第一表面，并且电极包括第二表面。在该实施例中，电极的第二表面耦合到MTJ元件的第一表面，使得形成界面区域，并且界面面积小于第一表面积。

76. 发明授权

US07667247B2 Method for passivating gate dielectric films 有权
标题翻译：钝化栅介质膜的方法
公开(公告)号：US07667247B2
公开(公告)日：2010-02-23
申请号：US11745862
申请日：2007-05-08
申请人： Ching-Ya Wang , Wen-Chin Lee , Denny Tang
发明人： Ching-Ya Wang , Wen-Chin Lee , Denny Tang
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L21/28185 , H01L21/2822 , H01L29/51
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成电介质层，用含碳基团处理电介质层，在经处理的电介质层上形成导电层，以及图案化和蚀刻电介质层和导电层以形成门结构。含碳基团包括OCH 3或CN物质。

77. 发明授权

US07579612B2 Resistive memory device having enhanced resist ratio and method of manufacturing same 有权
标题翻译：具有增强的抗蚀剂比率的电阻式存储器件及其制造方法
公开(公告)号：US07579612B2
公开(公告)日：2009-08-25
申请号：US11739942
申请日：2007-04-25
申请人： Denny Tang , Tai-Bor Wu , Wen-Yuan Chang , Tzyh-Cheang Lee
发明人： Denny Tang , Tai-Bor Wu , Wen-Yuan Chang , Tzyh-Cheang Lee
IPC分类号： H01L47/00
CPC分类号： G11C11/16 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/55
摘要： Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.
摘要翻译：这里公开了具有包围介电层的一个或多个缓冲层的新的电阻式存储器件。通过在器件的介电层周围插入一个或多个缓冲层，器件的电阻比被高度提高。例如，使用这种独特的堆叠结构的测试显示出比电阻式存储器件中发现的常规电极 - 电介质电极堆叠结构大约1000倍的电阻比。电阻式存储器件的电阻比的这种改进被认为是来自缓冲层和电介质层之间的改进的界面相干性，从而更平滑的形貌。

78. 发明授权

US07577020B2 System and method for reading multiple magnetic tunnel junctions with a single select transistor 有权
标题翻译：用单个选择晶体管读取多个磁隧道结的系统和方法
公开(公告)号：US07577020B2
公开(公告)日：2009-08-18
申请号：US11865481
申请日：2007-10-01
申请人： Shine Chung , Denny Tang , Fu-Lung Hsueh
发明人： Shine Chung , Denny Tang , Fu-Lung Hsueh
IPC分类号： G11C11/00 , G11C11/15 , G11C15/00
CPC分类号： G11C13/003 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C2213/75 , G11C2213/78
摘要： A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs.
摘要翻译：一种用于读取与选择晶体管串联连接以形成存储器串的两个或多个磁隧道结（MTJ）的方法，所述方法包括接通选择晶体管，测量存储器串的第一电阻，存储第一电阻，切换MTJ中的预定的一个，在切换之后测量存储器串的第二电阻，反转预定的一个MTJ，并用多个预定电阻值比较第一和第二电阻，其中比较结果导致确定存储在MTJ中的数据。

79. 发明授权

US07286429B1 High speed sensing amplifier for an MRAM cell 有权
标题翻译：用于MRAM单元的高速感测放大器
公开(公告)号：US07286429B1
公开(公告)日：2007-10-23
申请号：US11379854
申请日：2006-04-24
申请人： Jhon Jhy Liaw , Denny Tang
发明人： Jhon Jhy Liaw , Denny Tang
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C7/02 , G11C7/062 , G11C7/067 , G11C7/14 , G11C13/0004 , G11C13/004
摘要： A method and circuits are disclosed for sensing an output of a memory cell having high and low resistance states. A high reference cell is in high resistance state and a low reference cell is in low resistance state. The resistance of the high reference cell in high resistance state has a first margin of difference from the resistance of the memory cell in high resistance state. The resistance of the low reference cell in low resistance state has a second margin of difference from the resistance of the memory cell in low resistance state. Differential amplifiers coupled to the memory cell and the high and low reference cells provide a digital output representing the resistance state of the memory cell.
摘要翻译：公开了用于感测具有高和低电阻状态的存储单元的输出的方法和电路。高参考电池处于高电阻状态，低参考电池处于低电阻状态。高参考电池在高电阻状态下的电阻与高电阻状态下的存储单元的电阻具有第一差值。低电阻状态下的低参考电池的电阻与低电阻状态下的存储单元的电阻具有第二差值。耦合到存储器单元和高和低参考单元的差分放大器提供表示存储器单元的电阻状态的数字输出。

80. 发明申请

US20060039183A1 Multi-sensing level MRAM structures 审中-公开
标题翻译：多感测级MRAM结构
公开(公告)号：US20060039183A1
公开(公告)日：2006-02-23
申请号：US10850855
申请日：2004-05-21
申请人： Wen Lin , Denny Tang , Chien-Chung Hung , Wen-Chin Lee
发明人： Wen Lin , Denny Tang , Chien-Chung Hung , Wen-Chin Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/5607 , G11C11/16
摘要： A memory cell including a switching element having a source and a drain, a first magnetic tunnel junction (MTJ) device, and a second MTJ device. The first MTJ device has a first tunneling junction resistance and is coupled to a first one of the switching element source and drain. The second MTJ device has a second tunneling junction resistance and is coupled to a second one of the switching element source and drain. The second resistance is substantially less than the first resistance.
摘要翻译：一种存储单元，包括具有源极和漏极的开关元件，第一磁性隧道结（MTJ）器件和第二MTJ器件。第一MTJ器件具有第一隧道结电阻并且耦合到开关元件源极和漏极中的第一个。第二MTJ器件具有第二隧道结电阻并且耦合到开关元件源极和漏极中的第二个。第二阻力远小于第一阻力。

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