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71. 发明授权

US4751322A Monomer purification 失效
标题翻译：单体纯化
公开(公告)号：US4751322A
公开(公告)日：1988-06-14
申请号：US855965
申请日：1986-04-25
申请人： Stephen A. Fischer , Dinshaw F. Bardoliwalla , Reuben H. Grinstein , Gary L. Speenburgh
发明人： Stephen A. Fischer , Dinshaw F. Bardoliwalla , Reuben H. Grinstein , Gary L. Speenburgh
IPC分类号： C07C67/48
CPC分类号： C07C303/42
摘要： The monomer, trimethyl ammonium ethyl methacrylate methosulfate, is purified by passing same through a column of activated charcoal having a mean particle diameter of from about 0.5 mm to aboug 1.2 mm, the height to diameter ratio of the column being from about 3 to about 12 to 1. Monomer so treated can be polymerized to higher molecular weight polymers.
摘要翻译：通过将平均粒径为约0.5mm的活性炭柱通过相当于1.2mm的柱，柱的高度与直径之比为约3至约12，纯化单体，甲基丙烯酸三甲基铵甲基丙烯酸甲酯甲基硫酸铵如此处理的单体可以聚合成较高分子量的聚合物。

72. 发明授权

US4478795A Aluminum trihydroxide deliquoring with anionic polymers 失效
标题翻译：用阴离子聚合物脱铝三氢氧化铝
公开(公告)号：US4478795A
公开(公告)日：1984-10-23
申请号：US434934
申请日：1982-10-18
申请人： Maryellen Hereda , Stephen A. Fischer
发明人： Maryellen Hereda , Stephen A. Fischer
IPC分类号： C01F7/46 , C01F7/06
CPC分类号： C01F7/46
摘要： During the final stages of Al(OH).sub.3 production, deliquoring the aluminum trihydroxide slurry of excess sodium ions in the form of caustic liquor is conventionally achieved by numerous water washes prior to drying the product. Addition of an effective amount of highly charged, high molecular weight anionic polymer flocculant to the aluminum trihydroxide slurry improves the filtration rate, i.e., increases the amount and rate of removal of caustic liquor from the slurry. Addition of the flocculant reduces the amount of washing necessary to remove sodium ions from the final cake and also provides higher cake solids which results in greater production per unit time and less expenditure of energy in the drying process. Anionic polymers derived from 80 to 100% of an anionic vinyl monomer such as acrylic acid and from 20 to 0% of a nonionic vinyl monomer such as acrylamide having molecular weights between 1.5 to 12.0.times.10.sup.6 are useful in deliquoring aluminum trihydroxide slurries. Anionic polymer dosages of from about 150 to about 600 ppm may be used to treat 200 ml of about 5 to about 10% by weight of aluminum trihydroxide slurry. Higher dosages are required when aluminum trihydroxide concentrations are greater than 10% by weight.
摘要翻译：在Al（OH）3生产的最后阶段期间，以苛性液体形式过量的钠离子的三氢氧化铝浆料脱水通常在干燥产物之前通过许多水洗涤来实现。将有效量的高电荷，高分子量阴离子聚合物絮凝剂加入到三氢氧化铝浆中改善了过滤速率，即增加苛性液体从浆料中除去的量和速率。絮凝剂的添加减少了从最终的滤饼中除去钠离子所需的洗涤量，并且还提供了较高的饼状固体，这导致每单位时间的更大的产量和更少的干燥过程中的能量消耗。衍生自80至100％的阴离子乙烯基单体如丙烯酸和20至0％非离子乙烯基单体（如分子量为1.5至12.0×10 6的丙烯酰胺）的阴离子聚合物可用于脱铝三水合物浆料。可以使用约150至约600ppm的阴离子聚合物剂量来处理200ml约5至约10重量％的三氢氧化铝浆料。当三氢氧化铝浓度大于10重量％时，需要更高的剂量。

73. 发明授权

US09098268B2 MFENCE and LFENCE micro-architectural implementation method and system 有权
公开(公告)号：US09098268B2
公开(公告)日：2015-08-04
申请号：US13619832
申请日：2012-09-14
申请人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
发明人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Qawami
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

74. 发明申请

US20150055778A1 METHOD AND APPARATUS FOR A NON-DETERMINISTIC RANDOM BIT GENERATOR (NRBG) 有权
标题翻译：非确定性随机位发生器（NRBG）的方法和装置
公开(公告)号：US20150055778A1
公开(公告)日：2015-02-26
申请号：US13976175
申请日：2011-12-29
申请人： George W. Cox , David Johnston , Martin G. Dixon , Stephen A. Fischer , Jason W. Brandt
发明人： George W. Cox , David Johnston , Martin G. Dixon , Stephen A. Fischer , Jason W. Brandt
IPC分类号： H04L9/08 , G06F7/58
CPC分类号： H04L9/0869 , G06F7/588 , G06F9/30007 , H04L9/0662 , H04L2209/24
摘要： A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.
摘要翻译：提供了一种基于硬件的数字随机数发生器。在一个实施例中，处理器包括数字随机数发生器（DRNG），用于对熵源提供的熵数据进行条件生成，以产生多个确定性随机位（DRB）串，并产生多个非确定性随机位（NRB）响应于读取种子值的第一指令，从DRNG检索NRB字符串中的一个并将NRB字符串存储在由第一指令指定的目的地寄存器中，耦合到DRNG的执行单元。

75. 发明申请

US20150006938A1 Method And Apparatus For A Zero Voltage Processor 审中-公开
公开(公告)号：US20150006938A1
公开(公告)日：2015-01-01
申请号：US14254413
申请日：2014-04-16
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

76. 发明申请

US20140096247A1 Protection Against Return Oriented Programming Attacks 有权
标题翻译：防止面向导向的编程攻击
公开(公告)号：US20140096247A1
公开(公告)日：2014-04-03
申请号：US13799612
申请日：2013-03-13
申请人： Stephen A. Fischer
发明人： Stephen A. Fischer
IPC分类号： H04L29/06
CPC分类号： G06F21/566 , G06F21/52 , G06F2221/033 , H04L63/14
摘要： In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.
摘要翻译：在一个实施例中，处理器包括至少一个执行单元。处理器还包括耦合到至少一个执行单元的返向定向编程（ROP）逻辑。 ROP逻辑可以基于秘密ROP值来验证存储在调用堆栈上的返回指针。秘密ROP值只能由操作系统访问。

77. 发明申请

US20140096245A1 Protection Against Return Oriented Programming Attacks 有权
公开(公告)号：US20140096245A1
公开(公告)日：2014-04-03
申请号：US13631342
申请日：2012-09-28
申请人： Stephen A. Fischer
发明人： Stephen A. Fischer
IPC分类号： G06F21/56
CPC分类号： G06F21/566 , G06F21/52 , G06F2221/033 , H04L63/14
摘要： In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.

78. 发明申请

US20130205117A1 MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM 审中-公开
标题翻译： MFENCE和LFENCE微结构实现方法与系统
公开(公告)号：US20130205117A1
公开(公告)日：2013-08-08
申请号：US13838229
申请日：2013-03-15
申请人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Oawami
发明人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Oawami
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译：一种用于防止内存访问的系统和方法。存储器负载可以围栏，或者所有内存访问都可以被围起来。系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。存储器排序单元内的缓冲器被分配给该指令。比栅栏指令更新的访问指令被停止。旧的访问指令已逐渐退出。当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。

79. 发明申请

US20120191951A1 MFENCE and LFENCE Micro-Architectural Implementation Method and System 有权
标题翻译： MFENCE和LFENCE微建筑实施方法与系统
公开(公告)号：US20120191951A1
公开(公告)日：2012-07-26
申请号：US13440096
申请日：2012-04-05
申请人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Oawami
发明人： Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Oawami
IPC分类号： G06F9/312
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3012 , G06F9/30145 , G06F9/3808 , G06F9/3812 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F2009/45583 , G06F2009/45591
摘要： A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
摘要翻译：一种用于防止内存访问的系统和方法。存储器负载可以围栏，或者所有内存访问都可以被围起来。系统接收一个将内存访问指令分为较早访问和较新访问的防护指令。存储器排序单元内的缓冲器被分配给该指令。比栅栏指令更新的访问指令被停止。旧的访问指令已逐渐退出。当所有较旧的内存访问都已停用时，从缓冲区中分派防护指令。

80. 发明授权

US07664970B2 Method and apparatus for a zero voltage processor sleep state 有权
标题翻译：零电压处理器睡眠状态的方法和装置
公开(公告)号：US07664970B2
公开(公告)日：2010-02-16
申请号：US11323254
申请日：2005-12-30
申请人： Sanjeev Jahagirdar , George Varghese , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Navch , Shai Rotem
发明人： Sanjeev Jahagirdar , George Varghese , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Navch , Shai Rotem
IPC分类号： G06F1/00 , G06F1/26 , G06F15/00 , G06F11/00
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
摘要翻译：本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。处理器可以包括专用高速缓存存储器。电压调节器可以耦合到处理器以向处理器提供工作电压。在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。

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