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71. 发明授权

US4877483A Method for contact between two conductive or semi-conductive layers deposited on a substrate 失效
标题翻译：沉积在基底上的两个导电或半导体层之间的接触方法
公开(公告)号：US4877483A
公开(公告)日：1989-10-31
申请号：US212889
申请日：1988-06-29
申请人： Albert Bergemont , Richard Ferrant
发明人： Albert Bergemont , Richard Ferrant
IPC分类号： H01L23/522 , H01L21/31 , H01L21/768 , H01L21/8247 , H01L27/10 , H01L27/115
CPC分类号： H01L21/76834
摘要： A method of contact between two conductive or semiconductive layers deposited on a substrate is disclosed. The method comprises the following steps:the depositing and etching of a first layer,the depositing of an insulating layer under pressure and temperature conditions such that the insulating layer is thinned at the edges of the etched zones of the first layer as compared with the thickness on the surface of the substrate and on the surfaces of the etched zones of the first layer,the chemical etching of the insulating layer on a thickness at least equal to the thickness of the thinned layer but substantially smaller than the thickness elsewhere,the depositing and etching of the second conductive or semiconductive layer under pressure and temperature conditions leading to high covering capacity.
摘要翻译：公开了沉积在基底上的两个导电或半导体层之间的接触方法。该方法包括以下步骤：沉积和蚀刻第一层，在压力和温度条件下沉积绝缘层，使得绝缘层在第一层的蚀刻区域的边缘处变薄，与厚度在衬底的表面上和第一层的蚀刻区域的表面上，绝缘层的化学蚀刻的厚度至少等于薄层的厚度，但是基本上小于其他地方的厚度，沉积和在导致高覆盖能力的压力和温度条件下蚀刻第二导电层或半导体层。

72. 发明申请

US20120275253A1 DIFFERENTIAL SENSE AMPLIFIER WITHOUT DEDICATED PASS-GATE TRANSISTORS 有权
标题翻译：差分放大器，没有专用的门极晶体管
公开(公告)号：US20120275253A1
公开(公告)日：2012-11-01
申请号：US13456047
申请日：2012-04-25
申请人： Richard Ferrant , Roland Thewes
发明人： Richard Ferrant , Roland Thewes
IPC分类号： G11C7/08 , G11C7/06 , G11C7/12
CPC分类号： G11C7/065 , G11C11/4091 , G11C2207/002
摘要： A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-up transistors.
摘要翻译：一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端，以及具有连接到第二位线的输出和连接到第一位线的输入的第二CMOS反相器。每个CMOS反相器包括上拉晶体管和下拉晶体管，并且读出放大器具有一对传输栅晶体管，被布置为将第一和第二位线连接到第一和第二全局位线。有利的是，栅极晶体管由上拉晶体管或上拉晶体管构成。

73. 发明申请

US20120275252A1 DIFFERENTIAL SENSE AMPLIFIER WITHOUT SWITCH TRANSISTORS 有权
标题翻译：不带开关晶体管的差分放大器
公开(公告)号：US20120275252A1
公开(公告)日：2012-11-01
申请号：US13456020
申请日：2012-04-25
申请人： Richard Ferrant , Roland Thewes
发明人： Richard Ferrant , Roland Thewes
IPC分类号： G11C7/12 , G11C7/02
CPC分类号： G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2211/4016
摘要： A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.
摘要翻译：一种用于感测存储在存储单元阵列的多个存储单元中的数据的差分读出放大器，包括连接到第一位线（BL）的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入端位线和具有连接到第二位线（/ BL）的输出的第二CMOS反相器和连接到第一位线的输入。每个CMOS反相器包括上拉和下拉晶体管，其中上拉晶体管或下拉晶体管中的任一个的源极电耦合并连接到上拉电压源或下拉电压源，而没有在晶体管的源极和电压源之间的中间晶体管。

74. 发明授权

US07817466B2 Semiconductor array including a matrix of cells and a method of making a semiconductor array having a matrix of cells 有权
标题翻译：包括单元矩阵的半导体阵列和制造具有单元矩阵的半导体阵列的方法
公开(公告)号：US07817466B2
公开(公告)日：2010-10-19
申请号：US12130918
申请日：2008-05-30
申请人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
发明人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C2211/4016 , H01L21/8232 , H01L21/84 , H01L27/0207 , H01L27/10 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/115 , H01L27/11521 , H01L27/118 , H01L27/11803 , H01L27/12 , H01L27/1203 , H01L29/7841
摘要： A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
摘要翻译：半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。每个单元耦合到许多控制线，允许选择和读取/写入所述单元。所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

75. 发明申请

US20090125789A1 BUS WITH ERROR CORRECTION CIRCUITRY 有权
标题翻译：总线错误校正电路
公开(公告)号：US20090125789A1
公开(公告)日：2009-05-14
申请号：US12140643
申请日：2008-06-17
申请人： Richard Ferrant , Cedric Maufront
发明人： Richard Ferrant , Cedric Maufront
IPC分类号： G06F11/10
CPC分类号： H04L25/14 , H04L1/0043 , H04L2001/0094
摘要： A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.
摘要翻译：包括串联耦合的多个逻辑块的数据总线，每个逻辑块包括用于缓冲经由数据总线传输的至少一个数据位的至少一个缓冲器，以及至少一个逻辑块，还包括与该数据总线并联耦合的电路至少一个缓冲器，并被布置成确定与所述至少一个数据位相关联的纠错码的第一位。

76. 发明申请

US20090086535A1 SEMICONDUCTOR ARRAY 有权
标题翻译：半导体阵列
公开(公告)号：US20090086535A1
公开(公告)日：2009-04-02
申请号：US12130918
申请日：2008-05-30
申请人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
发明人： Richard Ferrant , Franck Genevaux , David Burnett , Gerald Gouya , Pierre Malinge
IPC分类号： G11C11/34
CPC分类号： H01L27/105 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C2211/4016 , H01L21/8232 , H01L21/84 , H01L27/0207 , H01L27/10 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10882 , H01L27/115 , H01L27/11521 , H01L27/118 , H01L27/11803 , H01L27/12 , H01L27/1203 , H01L29/7841
摘要： A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.
摘要翻译：半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。每个单元耦合到许多控制线，允许选择和读取/写入所述单元。所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

77. 发明授权

US07180801B2 Memory circuit with shared redundancy 有权
标题翻译：内存电路具有共享冗余
公开(公告)号：US07180801B2
公开(公告)日：2007-02-20
申请号：US10745294
申请日：2003-12-23
申请人： Richard Ferrant , François Jacquet , Laurent Murillo
发明人： Richard Ferrant , François Jacquet , Laurent Murillo
IPC分类号： G11C7/00
CPC分类号： G11C29/848 , G11C29/808
摘要： An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.
摘要翻译：一种集成电路存储器，包括至少两个存储体，每个存储体具有存储元件的阵列，所述存储元件阵列具有至少一个冗余列，并且每个与特定读出放大器相关联，每行与存储体共用的输入/输出缓冲器电路行以及每个存储体，用于将冗余列分配给连接到所述缓冲器之一的输入/输出线的电路。对于当前秩的行，可以针对前一列的列和朝向下一列的列执行分配。

78. 发明授权

US07130206B2 Content addressable memory cell including resistive memory elements 有权
标题翻译：内容可寻址存储单元，包括电阻存储元件
公开(公告)号：US07130206B2
公开(公告)日：2006-10-31
申请号：US10955836
申请日：2004-09-30
申请人： Richard Ferrant
发明人： Richard Ferrant
IPC分类号： G11C15/00 , G11C11/00
CPC分类号： G11C13/0004 , G11C15/02 , G11C15/046
摘要： A content addressable memory cell is described. In one embodiment, the content addressable memory cell includes first and second resistive memory elements being coupled in a first series connection and being connected between a first potential value and a second potential value being smaller than said first potential value, and means for their switching between states exhibiting different electric resistance values. The memory cell includes a first field effect transistor and a second field effect transistor, said first and second transistors having drain-source-paths and gate electrodes, said drain-source-paths of said first and second transistors being connected in a second series connection and being connected to at least one of first current lines. The first current line is connected to a potential value level detector for sensing a potential difference as to said third potential value.
摘要翻译：描述内容可寻址存储器单元。在一个实施例中，内容可寻址存储器单元包括第一和第二电阻存储器元件，其以第一串联连接耦合并连接在第一电位值和小于所述第一电位值的第二电位值之间，呈现不同电阻值的状态。存储单元包括第一场效应晶体管和第二场效应晶体管，所述第一和第二晶体管具有漏源路径和栅电极，所述第一和第二晶体管的所述漏源极路径以第二串联连接并且连接到第一电流线中的至少一个。第一电流线连接到电位值电平检测器，用于感测关于所述第三电位值的电位差。

79. 发明授权

US07068533B2 Resistive memory cell configuration and method for sensing resistance values 失效
标题翻译：电阻式存储单元配置及检测电阻值的方法
公开(公告)号：US07068533B2
公开(公告)日：2006-06-27
申请号：US10955832
申请日：2004-09-30
申请人： Richard Ferrant , Arkalgud Sitaram
发明人： Richard Ferrant , Arkalgud Sitaram
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C11/15
摘要： A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current lines; a plurality of second current lines; and a plurality of third current lines. A plurality of resistive memory cells being disposed in a memory matrix form between said first and second current lines, said first current lines defining the columns of said memory matrix form, while said second current lines defining the rows of it, wherein each one of the resistive memory cells being connected to one of said first current lines; a plurality of selection transistors having gates and drain-source paths, each drain-source path of said selection transistors being connected to a multiplicity of the resistive memory cells of a row of said memory matrix, said drain-source paths of different selection transistors being connected to a fourth current line (SL), the gates of said selection transistors of a row of said memory matrix form being connected to one of said third current lines. It further relates to a method for sensing the resistance values of a selected resistive memory cell.
摘要翻译：公开了一种电阻式存储单元的结构。在一个实施例中，电阻存储单元的配置包括多条第一电流线; 多条第二电流线; 和多条第三电流线。多个电阻存储器单元以所述第一和第二电流线之间的存储矩阵形式布置，所述第一电流线限定所述存储矩阵形式的列，而所述第二电流线限定其行，其中每个电阻存储器单元连接到所述第一电流线之一; 具有栅极和漏极 - 源极路径的多个选择晶体管，所述选择晶体管的每个漏 - 源路径连接到所述存储矩阵的行的多个电阻存储单元，所述不同选择晶体管的所述漏 - 源路径为连接到第四电流线（SL），所述存储矩阵形式的行的所述选择晶体管的栅极连接到所述第三电流线之一。本发明还涉及一种用于感测所选择的电阻性存储单元的电阻值的方法。

80. 发明授权

US06934202B2 Memory circuit with dynamic redundancy 有权
标题翻译：具有动态冗余的内存电路
公开(公告)号：US06934202B2
公开(公告)日：2005-08-23
申请号：US10345843
申请日：2003-01-16
申请人： Richard Ferrant
发明人： Richard Ferrant
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/848
摘要： The present invention relates to an integrated circuit including at least one matrix network of identical elements capable of being individually addressed at least in a first direction and including, at least for this first direction, at least one redundancy element, and a circuit that reversibly inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element. The integrated circuit also may include a circuit that definitely inhibits the operation of a defective element and maintains the circuit operation by using the redundancy element.
摘要翻译：本发明涉及一种集成电路，其包括至少一个相同元件的矩阵网络，能够至少在第一方向上被单独地寻址，并且至少包括至少对于该第一方向至少一个冗余元件，以及可逆地抑制故障元件的操作并通过使用冗余元件来维持电路操作。集成电路还可以包括绝对地禁止故障元件的操作并且通过使用冗余元件来维持电路操作的电路。

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