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71. 发明授权

US06501534B1 Automated periodic focus and exposure calibration of a lithography stepper 失效
标题翻译：光刻步进机的自动周期聚焦和曝光校准
公开(公告)号：US06501534B1
公开(公告)日：2002-12-31
申请号：US09845375
申请日：2001-04-30
申请人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Carmen Lapid Morales
发明人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Carmen Lapid Morales
IPC分类号： G03B2752
CPC分类号： G03F7/70516 , G03F7/70558 , G03F7/70625 , G03F7/70641
摘要： The present invention is directed to a system and a method for calibrating a lithography stepper system. The system includes a lithography stepper system, measurement system such as a scatterometry system, and a processor for correlating an ideal “golden standard” characterization signature to a test structure characterization data set, based on a plurality of focus and exposure conditions.
摘要翻译：本发明涉及用于校准光刻步进系统的系统和方法。该系统包括光刻步进系统，诸如散射测量系统的测量系统和用于基于多个焦点和曝光条件将理想“黄金标准”表征特征与测试结构表征数据集相关联的处理器。

72. 发明授权

US06465156B1 Method for mitigating formation of silicon grass 失效
标题翻译：降低硅草形成的方法
公开(公告)号：US06465156B1
公开(公告)日：2002-10-15
申请号：US09422390
申请日：1999-10-21
申请人： Bhanwar Singh , Bharath Rangarajan , Steven Avanzino
发明人： Bhanwar Singh , Bharath Rangarajan , Steven Avanzino
IPC分类号： G03F738
CPC分类号： G03F7/38 , G03F7/265
摘要： The present invention relates to a method for mitigating formation of silicon grass. A silylation process is performed on a semiconductor structure, the structure including a photoresist layer, an underlayer under the photoresist layer, and a substrate under the underlayer. A chemical mechanical polishing process is employed to remove a portion of the photoresist layer.
摘要翻译：本发明涉及减轻硅草的形成的方法。在半导体结构上进行甲硅烷化处理，该结构包括光致抗蚀剂层，光致抗蚀剂层下的底层和底层下的基底。采用化学机械抛光工艺去除一部分光致抗蚀剂层。

73. 发明授权

US06459945B1 System and method for facilitating determining suitable material layer thickness in a semiconductor device fabrication process 失效
标题翻译：用于在半导体器件制造工艺中有助于确定合适的材料层厚度的系统和方法
公开(公告)号：US06459945B1
公开(公告)日：2002-10-01
申请号：US09311223
申请日：1999-05-13
申请人： Bhanwar Singh , Carmen Morales , Bharath Rangarajan
发明人： Bhanwar Singh , Carmen Morales , Bharath Rangarajan
IPC分类号： G06F1900
CPC分类号： B24B37/013 , B24B49/04 , H01L21/67253 , H01L22/34
摘要： The present invention relates to a test wafer for use in optimizing a process. The test wafer includes a substrate and a material layer formed over the substrate, wherein the material layer includes N number of test regions (N being an integer greater than one). At least one of the test regions has a material layer thickness different from another of the test regions. A spindle drive system is also provided for driving at least one spindle. One end of the at least one spindle is coupled to a polishing pad, which is employed in forming the test regions.
摘要翻译：本发明涉及用于优化工艺的测试晶片。测试晶片包括衬底和形成在衬底上的材料层，其中材料层包括N个测试区域（N是大于1的整数）。测试区域中的至少一个具有与另一个测试区域不同的材料层厚度。还提供用于驱动至少一个主轴的主轴驱动系统。所述至少一个心轴的一端连接到用于形成所述测试区域的抛光垫。

74. 发明授权

US06458607B1 Using UV/VIS spectrophotometry to regulate developer solution during a development process 失效
标题翻译：在开发过程中使用UV / VIS分光光度法来调节显影剂溶液
公开(公告)号：US06458607B1
公开(公告)日：2002-10-01
申请号：US09911151
申请日：2001-07-23
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L2166
CPC分类号： H01L22/26
摘要： A system for regulating temperature of a developer is provided. The system includes a system for regulating in-situ developer temperature, comprising at least one lamp operative to heat a portion of a developer; a lamp driving system for driving the at least one lamp; a system for directing radiation to the portion of the developer; a measuring system comprising a UV/Vis spectrophotometry system for measuring parameters of the developer based on radiation reflected from the developer; and a processor operatively coupled to the measuring system and a lamp driving system, the processor receiving developer parameter data from the measuring system and the processor using the data to at least partially base control of the at least one lamp so as to regulate temperature of at least a portion of the developer
摘要翻译：提供了一种用于调节显影剂温度的系统。该系统包括用于调节原位显影剂温度的系统，其包括至少一个用于加热显影剂的一部分的灯; 用于驱动所述至少一个灯的灯驱动系统; 用于将辐射引导到显影剂的一部分的系统; 包括用于基于从显影剂反射的辐射来测量显影剂的参数的UV / Vis分光光度测量系统的测量系统; 以及可操作地耦合到所述测量系统和灯驱动系统的处理器，所述处理器从所述测量系统接收显影剂参数数据和所述处理器，所述处理器使用所述数据至少部分地对所述至少一个灯的控制进行基准，以便调节所述至少一个灯的温度至少一部分开发商

75. 发明授权

US06440289B1 Method for improving seed layer electroplating for semiconductor 有权
标题翻译：改善半导体种子层电镀的方法
公开(公告)号：US06440289B1
公开(公告)日：2002-08-27
申请号：US09285334
申请日：1999-04-02
申请人： Christy Mei-Chu Woo , Bhanwar Singh , Bharath Rangarajan
发明人： Christy Mei-Chu Woo , Bhanwar Singh , Bharath Rangarajan
IPC分类号： C25D712
CPC分类号： H01L21/76873 , C25D5/18 , C25D7/123 , H01L21/2885 , H01L21/76843 , H01L2221/1089
摘要： A method is provided of forming a semiconductor seed layer starting with a non-electrochemical deposition of an initial deposition of the seed layer. This is followed by a very slow deposition rate electrochemical deposition with an organic additive at the beginning of the plating process to overcome the initial thin seed coverage at the bottom and bottom sidewall of a feature. The electrochemical deposition plates at a very low rate initially followed by a low rate deposition to build up a thicker and more uniform seed layer at the bottom and bottom sidewall. In the meantime, this slow plating rate step only adds a small thickness to the top portion of the feature where non-electrochemical deposition seed coverage was initially thicker.
摘要翻译：提供一种形成半导体种子层的方法，其以非电化学沉积种子层的初始沉积开始。其次是在电镀工艺开始时用有机添加剂进行非常缓慢的沉积速率的电化学沉积，以克服特征底部和底部侧壁处的初始薄种子覆盖。电化学沉积板以非常低的速率开始，随后是低速沉积，以在底部和底部侧壁处建立更厚和更均匀的种子层。同时，这种缓慢电镀速率步骤仅在非电化学沉积种子覆盖率最初较厚的特征的顶部部分增加了小的厚度。

76. 发明授权

US06372614B1 Dual damascene method for backened metallization using poly stop layers 有权
公开(公告)号：US06372614B1
公开(公告)日：2002-04-16
申请号：US09861748
申请日：2001-05-19
申请人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
发明人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L214763
摘要： A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

77. 发明授权

US06339955B1 Thickness measurement using AFM for next generation lithography 失效
标题翻译：厚度测量采用AFM进行下一代光刻
公开(公告)号：US06339955B1
公开(公告)日：2002-01-22
申请号：US09540251
申请日：2000-03-31
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G01B528
CPC分类号： G01B21/18 , G01B7/066 , G01B21/08 , G01Q30/04 , G01Q80/00 , H01L22/12 , Y10S977/852
摘要： The present invention relates to a method of determining a film thickness and comprises identifying a depth associated with a defect in an underlying material and forming the film over the underlying material. The method further comprises identifying a depth associated with the defect in the film and then using the identified depths to determine the film thickness. The present invention also relates to a system for determining a film thickness and comprises a defect inspection tool operable to identify a location of one or more defects in an underlying material and a topology measurement tool operable to measure a change in topology of a surface. The system also comprises a controller operably coupled to the defect inspection tool and the topology measurement tool. The controller is adapted to receive location information from the defect inspection tool relating to the one or more defects and use the location information to generate and transmit one or more control signals to the topology measurement tool to evaluate a topology of an underlying material and a film at the location corresponding to the one or more defect to thereby generate topology information. Lastly, the controller is adapted to receive the topology information form the topology measurement tool and determine a film thickness using the topology information.
摘要翻译：本发明涉及一种确定膜厚度的方法，包括确定与下层材料中的缺陷有关的深度并在下面的材料上形成薄膜。该方法还包括识别与薄膜中的缺陷相关联的深度，然后使用所识别的深度来确定膜厚度。本发明还涉及一种用于确定膜厚度的系统，并且包括可操作以识别下层材料中的一个或多个缺陷的位置的缺陷检查工具和可操作以测量表面拓扑变化的拓扑测量工具。该系统还包括可操作地耦合到缺陷检查工具和拓扑测量工具的控制器。所述控制器适于接收来自所述缺陷检查工具的与所述一个或多个缺陷有关的位置信息，并使用所述位置信息来生成并发送一个或多个控制信号到所述拓扑测量工具以评估下面的材料和电影的拓扑在与一个或多个缺陷相对应的位置处，从而生成拓扑信息。最后，控制器适于从拓扑测量工具接收拓扑信息，并使用拓扑信息确定膜厚度。

78. 发明授权

US06270579B1 Nozzle arm movement for resist development 有权
标题翻译：喷嘴臂运动用于抗蚀剂开发
公开(公告)号：US06270579B1
公开(公告)日：2001-08-07
申请号：US09429995
申请日：1999-10-29
申请人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Michael K. Templeton , Sanjay K. Yedur
发明人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Michael K. Templeton , Sanjay K. Yedur
IPC分类号： B05C1102
CPC分类号： H01L21/6715 , G03F7/3028
摘要： A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied. The thickness uniformity data can also be used to adjust the volume of developer applied along the path and/or the volume flow rate.
摘要翻译：提供了一种有助于在光致抗蚀剂材料层上施加均匀的显影剂材料层的系统和方法。该系统包括多个尖端喷嘴和运动系统，该运动系统将喷嘴移动到位于基板上的光致抗蚀剂材料层的中心区域上方的操作位置，并且当喷嘴扫描移动穿过预定路径时施加一定体积的显影剂。移动系统通过提供具有第一臂构件的臂来移动喷嘴，该臂具有可围绕第一旋转轴线枢转的第一臂构件和可围绕第二旋转轴线枢转或可沿着平移轴线移动的第二臂构件。该系统还提供了测量设置在测试晶片上的显影的光致抗蚀剂材料层的厚度均匀性的测量系统。当施加显影剂时，厚度均匀性数据用于重新配置喷嘴的预定路径。厚度均匀性数据也可用于调节沿路径施加的显影剂的体积和/或体积流量。

79. 发明授权

US06251570B1 Resist developer saving system using material to reduce surface tension and wet resist surface 有权
标题翻译：抵抗使用材料的显影剂储存系统，以减少表面张力和抗湿表面
公开(公告)号：US06251570B1
公开(公告)日：2001-06-26
申请号：US09604372
申请日：2000-06-27
申请人： Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Bhanwar Singh
IPC分类号： G03F732
CPC分类号： G03F7/32 , G03F7/322 , G03F7/38
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving the steps of exposing the semiconductor structure including the resist to acting radiation; contacting the semiconductor structure including the exposed resist with a solution comprising water and from about 0.01% to about 5% by weight of a surfactant; and developing the resist with a developer.
摘要翻译：在一个实施例中，本发明涉及一种处理包括其上的抗蚀剂的半导体结构的方法，包括将包括抗蚀剂的半导体结构暴露于作用辐射的步骤; 将包含曝光的抗蚀剂的半导体结构与包含水和约0.01重量％至约5重量％的表面活性剂的溶液接触; 并用开发商开发抗蚀剂。

80. 发明授权

US06187666B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06187666B1
公开(公告)日：2001-02-13
申请号：US09328148
申请日：1999-06-08
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

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