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71. 发明申请

US20060152962A1 Integrated DRAM-NVRAM multi-level memory 失效
公开(公告)号：US20060152962A1
公开(公告)日：2006-07-13
申请号：US11368202
申请日：2006-03-03
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： G11C11/24
CPC分类号： G11C14/00 , G11C11/5621 , G11C11/5671 , G11C14/0018
摘要： An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

72. 发明申请

US20060146605A1 Integrated DRAM-NVRAM multi-level memory 有权
公开(公告)号：US20060146605A1
公开(公告)日：2006-07-06
申请号：US11367859
申请日：2006-03-03
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C14/00 , G11C11/5621 , G11C11/5671 , G11C14/0018
摘要： An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

73. 发明申请

US20120181662A1 LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES 有权
标题翻译：具有控制接口的LANTHANIDE电介质
公开(公告)号：US20120181662A1
公开(公告)日：2012-07-19
申请号：US13430098
申请日：2012-03-26
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L21/3141 , H01G4/08 , H01L21/28194 , H01L21/316 , H01L28/40 , H01L29/513 , H01L29/517
摘要： Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.
摘要翻译：提供电介质的方法和装置。一个方法实施例包括在衬底上形成钝化层，其中钝化层含有硅，氧和氮的组成。该方法还包括在钝化层上形成镧系元素介电膜，并在镧系元素介电膜上形成封装层。

74. 发明申请

US20120139004A1 HIGH-PERFORMANCE ONE-TRANSISTOR MEMORY CELL 审中-公开
标题翻译：高性能单晶体管存储单元
公开(公告)号：US20120139004A1
公开(公告)日：2012-06-07
申请号：US13368535
申请日：2012-02-08
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/78
CPC分类号： H01L27/108 , G11C11/40 , G11C11/404 , H01L21/84 , H01L27/1021 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein.
摘要翻译：本公开的一个方面涉及存储器单元。在各种实施例中，存储单元包括具有浮动节点的存取晶体管和连接在浮动节点和二极管参考电位线之间的二极管。二极管包括阳极，阴极和阳极和阴极之间的本征区域。表示存储单元的存储状态的电荷被保持在二极管的本征区域的两侧。在各种实施例中，存储器单元以体半导体技术实现。在各种实施例中，存储器单元以绝缘体上半导体技术实现。在各种实施例中，二极管是栅极控制的。在各种实施例中，通过在SOI存取晶体管的浮体中有意产生的电荷对二极管进行充电。各种实施例包括横向取向的二极管（堆叠和平面配置），并且各种实施例包括垂直取向的二极管。本文提供了其它方面和实施例。

75. 发明授权

US08058118B2 Methods of forming and operating back-side trap non-volatile memory cells 有权
标题翻译：形成和操作背面陷阱非易失性存储单元的方法
公开(公告)号：US08058118B2
公开(公告)日：2011-11-15
申请号：US12956570
申请日：2010-11-30
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/74
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/0416 , G11C16/0483 , H01L21/28273 , H01L21/84 , H01L27/11521 , H01L29/4232 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： Methods of forming and operating a back-side trap non-volatile memory cell. Method of forming a back-side trap non-volatile memory cell include forming a trapping material, forming two or more sub-layers of dielectric material on the trapping material, wherein a conduction band offset of each sub-layer of dielectric material is less than the conduction band offset of the material upon which it is formed, and forming a channel region on the two or more sub-layers of dielectric material. Methods of operating a back-side trap non-volatile memory cell include programming the memory cell via direct tunneling of carriers through an asymmetric band-gap tunnel insulator layer having two or more sub-layers formed beneath a channel region and having layers of material of increasing conduction band offset, and trapping the carriers in a trapping layer formed under the tunnel insulator layer.
摘要翻译：形成和操作背面陷阱非易失性存储单元的方法。形成背面陷阱非易失性存储单元的方法包括形成捕获材料，在捕获材料上形成介电材料的两个或多个子层，其中介电材料的每个子层的导带偏移小于其形成的材料的导带偏移，并且在介电材料的两个或更多个子层上形成沟道区。操作背面陷阱非易失性存储器单元的方法包括通过载流子的直接隧道通过具有形成在沟道区下面的具有两个或多个子层的非对称带隙隧道绝缘体层来编程存储单元，并且具有增加导带偏移，并将载流子俘获在形成在隧道绝缘体层之下的俘获层中。

76. 发明申请

US20110134691A1 SCALABLE MULTI-FUNCTION AND MULTI-LEVEL NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：可扩展的多功能和多级纳米晶体非易失性存储器件
公开(公告)号：US20110134691A1
公开(公告)日：2011-06-09
申请号：US13027573
申请日：2011-02-15
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： G11C11/34 , H01L21/336 , B82Y40/00
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/10 , H01L27/115 , H01L29/42332 , H01L29/513
摘要： A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.
摘要翻译：多功能和多层存储单元包括在衬底上形成的隧道层。在一个实施例中，隧道层包括两层，例如HfO 2和LaAlO 3。在隧道层上形成电荷阻挡层。在一个实施方案中，该层由HfSiON形成。控制栅极形成在电荷阻挡层上。离散的捕获层嵌入在隧道层或电荷阻挡层中，这取决于期望的非挥发性水平。离散捕获层越靠近衬底/绝缘体界面，器件的非易失性越低。离散捕获层由具有均匀尺寸和分布的纳米晶体形成。

77. 发明授权

US07867850B2 Enhanced multi-bit non-volatile memory device with resonant tunnel barrier 有权
标题翻译：具有谐振隧道势垒的增强型多位非易失性存储器件
公开(公告)号：US07867850B2
公开(公告)日：2011-01-11
申请号：US12349133
申请日：2009-01-06
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , G11C11/56 , G11C16/0466 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/792
摘要： A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO3. A charge trapping layer is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge trapping layer. A control gate is formed over the charge blocking layer. Another embodiment forms a floating gate over the tunnel barrier that is comprised of two oxide layers with an amorphous layer of silicon and/or germanium between the oxide layers.
摘要翻译：非易失性存储单元使用在两层HfSiON或LaAlO 3之间具有非晶硅和/或无定形锗层的谐振隧道势垒。在隧道势垒上形成电荷俘获层。在电荷捕获层上形成高k电荷阻挡层。控制栅极形成在电荷阻挡层上。另一个实施例在隧道势垒上形成浮动栅极，该栅极由在氧化物层之间具有硅和/或锗的非晶层的两个氧化物层组成。

78. 发明授权

US07851850B2 Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection 有权
标题翻译：利用增强栅极注入的带状工程纳米晶体非易失性存储器件
公开(公告)号：US07851850B2
公开(公告)日：2010-12-14
申请号：US12623895
申请日：2009-11-23
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , G11C16/0416 , G11C16/0483 , G11C2216/06 , H01L29/513 , H01L29/7883
摘要： Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.
摘要翻译：描述了使用具有带工程化栅极堆叠的反向模式非易失性存储器单元和在EEPROM和块可擦除存储器件（例如闪存器件）中的纳米晶体电荷俘获的非易失性存储器件和阵列。本发明的实施例允许使用控制门的反向模式栅极 - 绝缘体堆叠存储器单元来编程和擦除通过波段设计的波峰隧道势垒。通过在非导电捕获层和高K介电电荷阻挡层中利用高功函数纳米晶体来提高电荷保持率。具有本发明实施例的非易失性存储单元的具有对称或非对称顶点势垒隧道层的带隙工程的栅极叠层允许用电子和空穴进行低电压隧道编程和擦除，同时保持高电荷阻挡屏障和深度载体捕获位点，保持良好的电荷。

79. 发明申请

US20100308389A1 DISCRETE TRAP NON-VOLATILE MULTI-FUNCTIONAL MEMORY DEVICE 有权
标题翻译：离散跟踪非易失性多功能存储器件
公开(公告)号：US20100308389A1
公开(公告)日：2010-12-09
申请号：US12857026
申请日：2010-08-16
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/94 , H01L29/792
CPC分类号： H01L29/511 , G11C11/005 , G11C14/0018 , H01L27/108 , H01L27/10873 , H01L27/115 , H01L29/792
摘要： A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.
摘要翻译：在衬底和离散陷阱层之间制造多层隧道绝缘体。多层的属性决定了存储器件的易失性。调整各层的组成和/或层的数量以同时制造DRAM器件，非易失性存储器件或两者。

80. 发明申请

US20100295118A1 Nanocrystal Based Universal Memory Cells, and Memory Cells 有权
标题翻译：基于纳米晶体的通用存储单元和存储单元
公开(公告)号：US20100295118A1
公开(公告)日：2010-11-25
申请号：US12815109
申请日：2010-06-14
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/792
CPC分类号： B82Y30/00 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/42332 , H01L29/42348 , H01L29/513 , H01L29/7881 , H01L29/792 , Y10S977/777 , Y10S977/943
摘要： Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.
摘要翻译：一些实施例包括包含动态随机存取存储器（DRAM）元件和非易失性存储器（NVM）元件的存储器单元。 DRAM元件包含功能不同的两种类型的DRAM纳米粒子。 NVM包含捕获深度不同的两种类型的NVM纳米颗粒。 NVM纳米颗粒可以在垂直移位的电荷捕获平面中。存储单元包含隧道电介质，并且NVM的电荷俘获平面之一可以比隧道电介质更远。距离隧道电介质更远的NVM电荷捕获平面可能包含比其他NVM电荷捕获平面更大的NVM纳米颗粒。 DRAM元件可以包含在其中具有两种类型的DRAM纳米颗粒的单个电荷捕获平面。存储器单元可以并入到电子系统中。

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