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71. 发明授权

US08015364B2 Method and apparatus for filtering snoop requests using a scoreboard 有权
标题翻译：使用记分板过滤窥探请求的方法和装置
公开(公告)号：US08015364B2
公开(公告)日：2011-09-06
申请号：US12129289
申请日：2008-05-29
申请人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another processor, to determine if a request is to be forwarded to the processor or, discarded. At least one scoreboard is active, and at least one scoreboard is determined to be historic at any point in time. A snoop determination of the queue indicates that an entry may be in the cache, but does not indicate its actual residence status. In addition, the snoop filter block implementing scoreboard data structures is operatively coupled with a cache wrap detection logic means whereby, upon detection of a cache wrap condition, the content of the active scoreboard is copied into a historic scoreboard and the content of at least one active scoreboard is reset.
摘要翻译：用于实现窥探高速缓存一致性的装置，其本地地减少呈现给多处理器系统中的每个缓存的窥探请求的数量。与单个处理器相关联的窥探过滤器装置包括一个或多个“记分板”数据结构，其进行窥探确定，即，来自另一个处理器的每个窥探请求，以确定请求是否被转发到处理器或被丢弃。至少一个记分牌是活跃的，并且至少一个记分牌被确定为在任何时间点的历史。队列的窥探确定表示一个条目可能在缓存中，但不表示其实际居住状态。此外，实现记分板数据结构的窥探过滤器块与高速缓存包检测逻辑装置可操作地耦合，由此在检测到缓存包装条件时，将活动记分板的内容复制到历史记分板中，并且至少一个活动记分板重置。

72. 发明申请

US20110173399A1 DISTRIBUTED PARALLEL MESSAGING FOR MULTIPROCESSOR SYSTEMS 失效
标题翻译：用于多处理器系统的分布式并行消息传递
公开(公告)号：US20110173399A1
公开(公告)日：2011-07-14
申请号：US12693972
申请日：2010-01-26
申请人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Philip Heidelberger , Valentina Salapura , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/16 , G06F12/02 , G06F15/173 , G06F15/76 , G06F9/06
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network, multiple injection messaging engine units and reception messaging engine units, each implementing a DMA engine and each supporting both multiple packet injection into and multiple reception from a network, in parallel. The reception side of the messaging unit (MU) includes a switch interface enabling writing of data of a packet received from the network to the memory system. The transmission side of the messaging unit, includes switch interface for reading from the memory system when injecting packets into the network.
摘要翻译：一种并行计算系统中分布式并行消息传递的方法和装置。该装置在多处理器网络的每个节点处包括多个注入消息传递引擎单元和接收消息传递引擎单元，每个实现一个DMA引擎，并且每个支持同时支持来自网络的多个分组注入和多个接收。消息接收单元（MU）的接收侧包括能够将从网络接收到的分组的数据写入存储器系统的切换接口。消息传送单元的发送侧包括用于在将分组注入网络时从存储器系统读取的切换接口。

73. 发明授权

US07620756B2 Method and apparatus for updating wide storage array over a narrow bus 有权
标题翻译：用于在窄总线上更新宽存储阵列的方法和装置
公开(公告)号：US07620756B2
公开(公告)日：2009-11-17
申请号：US11507306
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m
摘要翻译：一种用于从窄总线（m位，其中m

74. 发明申请

US20090059955A1 SINGLE CHIP PROTOCOL CONVERTER 失效
标题翻译：单芯片协议转换器
公开(公告)号：US20090059955A1
公开(公告)日：2009-03-05
申请号：US12189675
申请日：2008-08-11
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/22
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单个集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

75. 发明授权

US07477644B2 Method and system of efficient packet reordering 失效
标题翻译：高效数据包重排序方法及系统
公开(公告)号：US07477644B2
公开(公告)日：2009-01-13
申请号：US10604557
申请日：2003-07-30
申请人： Christos J Georgiou , Valentina Salapura
发明人： Christos J Georgiou , Valentina Salapura
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/10 , H04L47/34
摘要： A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.
摘要翻译：提供了一种方法和系统来有效地排序通过网络接收的分组。该方法通过检测失序分组来检测一个或多个分组流的序列中断，并且将顺序分组的分段进入用于特定流的单独的存储区域，例如链表。传输队列和重排序表用于记录每个段的起始序列号。参考传输队列以定位从流的最低分组序列号开始的分段。与段相关联的分组按顺序传输。然后，重复地搜索传输队列用于相关联的分组链的传输的下一个最低分组序列号，直到传输队列被清空。

76. 发明申请

US20090007134A1 SHARED PERFORMANCE MONITOR IN A MULTIPROCESSOR SYSTEM 失效
标题翻译：多处理器系统中的共享性能监视器
公开(公告)号：US20090007134A1
公开(公告)日：2009-01-01
申请号：US11768777
申请日：2007-06-26
申请人： George Chiu , Alan G. Gara , Valentina Salapura
发明人： George Chiu , Alan G. Gara , Valentina Salapura
IPC分类号： G06F9/46
CPC分类号： G06F11/348 , G06F11/3409 , G06F2201/86 , G06F2201/88 , Y02D10/34
摘要： A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.
摘要翻译：用于监视在多处理器系统中发生的事件的性能的性能监视单元（PMU）和方法。多处理器系统包括多个处理器设备单元，用于产生表示处理器设备中事件发生的信号的每个处理器设备，以及用于性能监控的单个共享计数器资源。性能监视器单元由多处理器系统中的所有处理器核共享。 PMU包括：多个性能计数器，每个用于对表示来自多处理器系统中的一个或多个处理器单元的事件进行计数的信号; 以及多个输入装置，用于从所述多个处理器单元中的一个或多个处理器装置接收事件信号，所述多个输入装置可编程以选择事件信号以供所述多个性能计数器中的一个或多个用于计数，其中PMU在多处理单元之间或多处理系统中的一组处理器内共享。 PMU进一步被编程为监视从非处理器设备发出的事件信号。

77. 发明申请

US20090006692A1 METHOD AND APPARATUS FOR A CHOOSE-TWO MULTI-QUEUE ARBITER 失效
标题翻译：选择两个多队列ARBITER的方法和装置
公开(公告)号：US20090006692A1
公开(公告)日：2009-01-01
申请号：US11768799
申请日：2007-06-26
申请人： Matthias A. Blumrich , Valentina Salapura
发明人： Matthias A. Blumrich , Valentina Salapura
IPC分类号： G06F13/14
CPC分类号： G06F13/364
摘要： An apparatus and method for granting one or more requesting entities access to a resource in a predetermined time interval. The apparatus includes a first circuit receiving one or more request signals, and implementing logic for assigning a priority to the one or more request signals, and, generating a set of first_request signals based on the priorities assigned. One or more priority select circuits for receiving the set of first_request signals and generating corresponding one or more fixed grant signals representing one or more highest priority request signals when asserted during the predetermined time interval. A second circuit device receives the one or more fixed grant signals generates one or more grant signals associated with one or more highest priority request signals assigned, the grant signals for enabling one or more respective requesting entities access to the resource in the predetermined time interval, wherein the priority assigned to the one or more request signals changes each successive predetermined time interval. In one embodiment, the assigned priority is based on a numerical pattern, the first circuit changing the numerical pattern with respect to the first_request signals generated at each successive predetermined time interval.
摘要翻译：一种用于在预定时间间隔内授予一个或多个请求实体对资源的访问的装置和方法。该装置包括接收一个或多个请求信号的第一电路，以及实现用于为一个或多个请求信号分配优先级的逻辑，以及基于分配的优先级生成一组第一请求信号。一个或多个优先级选择电路，用于在所述预定时间间隔期间被断言时，接收所述第一请求信号集合并产生表示一个或多个最高优先级请求信号的对应的一个或多个固定许可信号。第二电路装置接收一个或多个固定许可信号，产生与分配的一个或多个最高优先级请求信号相关联的一个或多个授权信号，用于使一个或多个相应的请求实体在预定时间间隔内访问该资源的授权信号，其中分配给所述一个或多个请求信号的优先级改变每个连续的预定时间间隔。在一个实施例中，分配的优先级基于数字模式，第一电路相对于在每个连续的预定时间间隔产生的第一要求信号改变数字模式。

78. 发明申请

US20080294850A1 METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS USING A SCOREBOARD 有权
标题翻译：使用分光镜过滤SNOOP要求的方法和装置
公开(公告)号：US20080294850A1
公开(公告)日：2008-11-27
申请号：US12129289
申请日：2008-05-29
申请人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Thomas R. Puzak , Valentina Salapura
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： An apparatus for implementing snooping cache coherence that locally reduces the number of snoop requests presented to each cache in a multiprocessor system. A snoop filter device associated with a single processor includes one or more “scoreboard” data structures that make snoop determinations, i.e., for each snoop request from another processor, to determine if a request is to be forwarded to the processor or, discarded. At least one scoreboard is active, and at least one scoreboard is determined to be historic at any point in time. A snoop determination of the queue indicates that an entry may be in the cache, but does not indicate its actual residence status. In addition, the snoop filter block implementing scoreboard data structures is operatively coupled with a cache wrap detection logic means whereby, upon detection of a cache wrap condition, the content of the active scoreboard is copied into a historic scoreboard and the content of at least one active scoreboard is reset.
摘要翻译：用于实现窥探高速缓存一致性的装置，其本地地减少呈现给多处理器系统中的每个缓存的窥探请求的数量。与单个处理器相关联的窥探过滤器装置包括一个或多个“记分板”数据结构，其进行窥探确定，即，来自另一个处理器的每个窥探请求，以确定请求是否被转发到处理器或被丢弃。至少一个记分牌是活跃的，并且至少一个记分牌被确定为在任何时间点的历史。队列的窥探确定表示一个条目可能在缓存中，但不表示其实际居住状态。此外，实现记分板数据结构的窥探过滤器块与高速缓存包检测逻辑装置可操作地耦合，由此在检测到缓存包装条件时，将活动记分板的内容复制到历史记分板中，并且至少一个活动记分板重置。

79. 发明申请

US20080244194A1 METHOD AND APARATHUS FOR FILTERING SNOOP REQUESTS USING STREAM REGISTERS 有权
标题翻译：使用流记录器过滤SNOOP要求的方法和方法
公开(公告)号：US20080244194A1
公开(公告)日：2008-10-02
申请号：US12137325
申请日：2008-06-11
申请人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0822 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one snoop filter primitive implementing filtering method based on usage of stream registers sets and associated stream register comparison logic. From the plurality of stream registers sets, at least one stream register set is active, and at least one stream register set is labeled historic at any point in time. In addition, the snoop filter block is operatively coupled with cache wrap detection logic whereby the content of the active stream register set is switched into a historic stream register set upon the cache wrap condition detection, and the content of at least one active stream register set is reset. Each filter primitive implements stream register comparison logic that determines whether a received snoop request is to be forwarded to the processor or discarded.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联的本地高速缓冲存储器。窥探过滤设备与每个处理单元相关联并且包括至少一个基于流寄存器集合和相关流寄存器比较逻辑的使用实现过滤方法的窥探过滤器原语。从多个流寄存器组中，至少一个流寄存器组是有效的，并且至少一个流寄存器集合在任何时间点被标记为历史。另外，监听滤波器块可操作地与高速缓存包检测逻辑耦合，从而将活动流寄存器集合的内容切换到在高速缓存环绕条件检测时设置的历史流寄存器，并且至少一个活动流寄存器集合的内容被复位。每个滤波器基元实现流寄存器比较逻辑，其确定接收的窥探请求是否被转发到处理器或丢弃。

80. 发明授权

US07392351B2 Method and apparatus for filtering snoop requests using stream registers 有权
标题翻译：使用流寄存器对窥探请求进行过滤的方法和装置
公开(公告)号：US07392351B2
公开(公告)日：2008-06-24
申请号：US11093130
申请日：2005-03-29
申请人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/0822 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one snoop filter primitive implementing filtering method based on usage of stream registers sets and associated stream register comparison logic. From the plurality of stream registers sets, at least one stream register set is active, and at least one stream register set is labeled historic at any point in time. In addition, the snoop filter block is operatively coupled with cache wrap detection logic whereby the content of the active stream register set is switched into a historic stream register set upon the cache wrap condition detection, and the content of at least one active stream register set is reset. Each filter primitive implements stream register comparison logic that determines whether a received snoop request is to be forwarded to the processor or discarded.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联的本地高速缓冲存储器。窥探过滤设备与每个处理单元相关联并且包括至少一个基于流寄存器集合和相关流寄存器比较逻辑的使用实现过滤方法的窥探过滤器原语。从多个流寄存器组中，至少一个流寄存器组是有效的，并且至少一个流寄存器集合在任何时间点被标记为历史。另外，监听滤波器块可操作地与高速缓存包检测逻辑耦合，从而将活动流寄存器集合的内容切换到在高速缓存环绕条件检测时设置的历史流寄存器，并且至少一个活动流寄存器集合的内容被复位。每个滤波器基元实现流寄存器比较逻辑，其确定接收的窥探请求是否被转发到处理器或丢弃。

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