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71. 发明授权

US08168499B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08168499B2
公开(公告)日：2012-05-01
申请号：US12662581
申请日：2010-04-23
申请人： Masato Koyama , Yoshinori Tsuchiya , Seiji Inumiya
发明人： Masato Koyama , Yoshinori Tsuchiya , Seiji Inumiya
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/823835 , H01L21/823857 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si
摘要翻译：可以提供一种半导体器件的制造方法，该半导体器件包括具有低阈值电压Vth和Ni-FUSI / SiON或高k栅极绝缘膜结构的CMIS。该方法包括：在衬底中形成彼此绝缘的p型半导体区域和n型半导体区域; 在p型和n型半导体区分别形成第一和第二栅极绝缘膜; 在所述第一栅极绝缘膜上方形成具有Ni / Si <31/12的组成的第一硅化镍和在所述第二栅极绝缘膜上具有Ni /Si≥31/ 12的组成的第二硅化镍; 以及通过使铝通过第一硅化镍扩散，在第一硅化镍和第一栅极绝缘膜之间的界面处分离铝。

72. 发明授权

US08076732B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08076732B2
公开(公告)日：2011-12-13
申请号：US12491728
申请日：2009-06-25
申请人： Reika Ichihara , Masato Koyama
发明人： Reika Ichihara , Masato Koyama
IPC分类号： H01L21/8238
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一种属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

73. 发明授权

US07804145B2 Semiconductor device, capacitor, and field effect transistor 有权
标题翻译：半导体器件，电容器和场效应晶体管
公开(公告)号：US07804145B2
公开(公告)日：2010-09-28
申请号：US12388810
申请日：2009-02-19
申请人： Tatsuo Shimizu , Masato Koyama
发明人： Tatsuo Shimizu , Masato Koyama
IPC分类号： H01L29/76
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L28/56 , H01L28/75 , H01L29/517 , H01L29/66833 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： It is made possible to provide a semiconductor device that has the effective work function of the connected metal optimized at the interface between a semiconductor and the metal. A semiconductor device includes: a semiconductor film; an oxide film formed on the semiconductor film, the oxide film including at least one of Hf and Zr, and at least one element selected from the group consisting of V, Cr, Mn, Nb, Mo, Tc, W, and Re being added to the oxide film; and a metal film formed on the oxide film.
摘要翻译：可以提供一种具有在半导体和金属之间的界面处优化的连接金属的有效功函数的半导体器件。半导体器件包括：半导体膜; 形成在半导体膜上的氧化物膜，包括Hf和Zr中的至少一种的氧化物膜和选自V，Cr，Mn，Nb，Mo，Tc，W和Re中的至少一种元素被添加到氧化膜; 和形成在氧化物膜上的金属膜。

74. 发明授权

US07727832B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US07727832B2
公开(公告)日：2010-06-01
申请号：US11907353
申请日：2007-10-11
申请人： Masato Koyama , Yoshinori Tsuchiya , Seiji Inumiya
发明人： Masato Koyama , Yoshinori Tsuchiya , Seiji Inumiya
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/823835 , H01L21/823857 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： It is made possible to provide a method for manufacturing a semiconductor device that includes CMISs each having a low threshold voltage Vth and a Ni-FUSI/SiON or high-k gate insulating film structure. The method comprises: forming a p-type semiconductor region and an n-type semiconductor region insulated from each other in a substrate; forming a first and second gate insulating films on the p-type and n-type semiconductor regions, respectively; forming a first nickel silicide having a composition of Ni/Si

75. 发明申请

US20100035392A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100035392A1
公开(公告)日：2010-02-11
申请号：US12549308
申请日：2009-08-27
申请人： Yoshinori Tsuchiya , Masato Koyama
发明人： Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L21/8234
CPC分类号： H01L29/4958 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/76802 , H01L21/76877 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/4966 , H01L29/4975 , H01L29/665
摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
摘要翻译：半导体器件包括具有半导体层，栅电极，源极区，漏极区，元件隔离绝缘膜层和布线的半导体衬底。栅极包括在半导体层上形成有栅极绝缘膜的层压结构，形成在栅极绝缘膜上的金属或金属化合物以及形成在金属或金属化合物上的多晶硅层。源极区域和漏极区域形成在半导体衬底的表面部分上，并将栅电极夹在其间。元件分离绝缘膜层围绕半导体层。布线与栅电极的金属或金属化合物接触。

76. 发明申请

US20090321844A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090321844A1
公开(公告)日：2009-12-31
申请号：US12491728
申请日：2009-06-25
申请人： Reika Ichihara , Masato Koyama
发明人： Reika Ichihara , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823842 , H01L29/4966 , H01L29/518 , H01L29/6659
摘要： A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.
摘要翻译：半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一个属于IIA族金属元素的第一上部金属层和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层层。第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

77. 发明授权

US07601623B2 Method of manufacturing a semiconductor device with a gate electrode having a laminate structure 有权
标题翻译：制造具有层叠结构的栅电极的半导体器件的制造方法
公开(公告)号：US07601623B2
公开(公告)日：2009-10-13
申请号：US12219096
申请日：2008-07-16
申请人： Yoshinori Tsuchiya , Masato Koyama
发明人： Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/4958 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/76802 , H01L21/76877 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/4966 , H01L29/4975 , H01L29/665
摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.
摘要翻译：半导体器件包括具有半导体层，栅电极，源极区，漏极区，元件隔离绝缘膜层和布线的半导体衬底。栅极包括在半导体层上形成有栅极绝缘膜的层压结构，形成在栅极绝缘膜上的金属或金属化合物以及形成在金属或金属化合物上的多晶硅层。源极区域和漏极区域形成在半导体衬底的表面部分上，并将栅电极夹在其间。元件分离绝缘膜层围绕半导体层。布线与栅电极的金属或金属化合物接触。

78. 发明授权

US07569891B2 Semiconductor device with reduced contact resistance and method for manufacturing the same 失效
标题翻译：具有降低的接触电阻的半导体器件及其制造方法
公开(公告)号：US07569891B2
公开(公告)日：2009-08-04
申请号：US11709857
申请日：2007-02-23
申请人： Yoshinori Tsuchiya , Masato Koyama
发明人： Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28052 , H01L21/28518 , H01L21/823835 , H01L21/823842 , H01L29/665
摘要： It is made possible to reduce the contact resistance of the source and drain in an n-type MISFET. A semiconductor device includes: a source and drain regions provided in a p-type semiconductor substrate so as to separate each other, each including: a silicide layer containing a first metal element as a main component having a vacuum work function of 4.6 eV or greater; and a layer containing at least one second metal element selected from the group of scandium elements and lanthanoid, the layer containing the second metal element including a segregating layer in which the highest areal density is 1×1014 cm−2 or higher, each region of the segregating layer with areal density of 1×1014 cm−2 or higher having a thickness smaller than 1 nm; a gate insulating film provided a region between the source and drain regions on the semiconductor substrate; and a gate electrode provided on the gate insulating film.
摘要翻译：可以降低n型MISFET中的源极和漏极的接触电阻。半导体器件包括：源区和漏区，设置在p型半导体衬底中以彼此分离，每个包括：含有第一金属元素作为主要成分的硅化物层，其真空功函数为4.6eV或更大 ; 以及包含选自钪元素和镧系元素的至少一种第二金属元素的层，所述第二金属元素的层包含其中最高面密度为1×10 14 cm -2以上的偏析层，所述偏析层的每个区域层，其面密度为1×10 14 cm -2以上，厚度小于1nm; 栅绝缘膜设置在半导体衬底上的源区和漏区之间的区域; 以及设置在栅极绝缘膜上的栅电极。

79. 发明申请

US20090114995A1 COMPLEMENTARY SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：补充半导体器件及其制造方法
公开(公告)号：US20090114995A1
公开(公告)日：2009-05-07
申请号：US12200599
申请日：2008-08-28
申请人： Masamichi Suzuki , Masato Koyama , Yoshinori Tsuchiya , Hirotaka Nishino , Reika Ichihara , Akira Takashima
发明人： Masamichi Suzuki , Masato Koyama , Yoshinori Tsuchiya , Hirotaka Nishino , Reika Ichihara , Akira Takashima
IPC分类号： H01L27/08 , H01L21/3205
CPC分类号： H01L21/823857 , H01L21/26506 , H01L21/31155 , H01L21/823842 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7842 , H01L29/7846 , H01L29/785
摘要： A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.
摘要翻译：互补半导体器件包括半导体衬底，形成在半导体衬底的表面上的第一半导体区域，形成在半导体衬底的离开第一半导体区域的表面上的第二半导体区域，具有第一栅极的n-MIS晶体管形成在第一半导体区域上的包括La和Al的绝缘膜和形成在栅极绝缘膜上的第一栅电极和形成在第二半导体区上的具有包括La和Al的第二栅极绝缘膜的p-MIS晶体管，以及形成在所述栅极绝缘膜上的第二栅电极，所述第二栅极绝缘膜中的原子密度比Al / La大于所述第一栅极绝缘膜中的原子密度比Al / La。

80. 发明申请

US20080237727A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20080237727A1
公开(公告)日：2008-10-02
申请号：US11965563
申请日：2007-12-27
申请人： Reika ICHIHARA , Yoshinori Tsuchiya , Masato Koyama
发明人： Reika ICHIHARA , Yoshinori Tsuchiya , Masato Koyama
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823842
摘要： The present invention provides a CMIS device that achieves a low threshold voltage by use of a metal gate superior in the resistance to annealing in a reducing atmosphere. The CMIS device includes a substrate, PMISFET and NMISFET. THE PMISFET includes: an N-type semiconductor layer formed on the substrate; first source/drain regions formed in the N-type semiconductor layer; a first gate insulating film formed on the N-type semiconductor layer between the first source/drain regions; a carbon layer formed on the first gate insulating film and having a thickness of 5 nanometers or smaller; a first gate electrode formed on the carbon layer and including a metal.
摘要翻译：本发明提供了一种CMIS器件，其通过使用在还原气氛中的退火电阻优异的金属栅极来实现低阈值电压。 CMIS器件包括衬底，PMISFET和NMISFET。 PMISFET包括：形成在衬底上的N型半导体层; 形成在N型半导体层中的第一源/漏区; 形成在所述第一源极/漏极区域之间的所述N型半导体层上的第一栅极绝缘膜; 形成在所述第一栅极绝缘膜上并具有5纳米或更小的厚度的碳层; 形成在碳层上并包括金属的第一栅电极。

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