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71. 发明授权

US07567584B2 Multiplex scheme conversion apparatus 有权
标题翻译：多路复用方案转换装置
公开(公告)号：US07567584B2
公开(公告)日：2009-07-28
申请号：US11033832
申请日：2005-01-13
申请人： Tadamasa Toma , Yoshinori Matsui
发明人： Tadamasa Toma , Yoshinori Matsui
IPC分类号： H04J3/14
CPC分类号： H04N21/2404 , H04N7/52 , H04N19/70 , H04N21/235 , H04N21/23608 , H04N21/435
摘要： A multiplex scheme conversion apparatus (103) includes (i) a packet loss judgment unit (202) that judges the packet loss of a TS packet, performs error processing in the case where a packet loss is detected, and outputs the payload data on which error processing has already been performed and (ii) a Box making unit (206) that makes ‘moov’ including error information and ‘mdat’ based on inputted AU data and the display time in a PES header.
摘要翻译：复用方案转换装置（103）包括：（i）判断TS分组的分组丢失的分组丢失判断单元（202），在检测到分组丢失的情况下执行错误处理，并输出其上的有效载荷数据已经执行了错误处理，以及（ii）根据输入的AU数据和PES头中的显示时间使“moov”包括错误信息和“mdat”的盒子制作单元（206）。

72. 发明申请

US20090122587A1 MEMORY SYSTEM AND DATA TRANSMISSION METHOD 失效
标题翻译：存储系统和数据传输方法
公开(公告)号：US20090122587A1
公开(公告)日：2009-05-14
申请号：US12270546
申请日：2008-11-13
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C5/02 , G11C7/00 , G11C5/06 , G06F1/12 , G11C8/18
CPC分类号： G11C7/1048 , G06F13/4243 , G06F13/4256 , G11C7/10 , G11C8/18 , G11C11/401 , G11C11/4093 , G11C29/028 , G11C29/50012
摘要： A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.
摘要翻译：可以通过减少由存储器控制器和存储器模块之间的各种布线中的分支和阻抗失配引起的反射信号等的影响以及由于数据的传输延迟，命令的影响而实现高速操作的存储系统 /地址和内存模块中的时钟。为此，存储器系统包括存储器控制器和安装有DRAM的存储器模块。缓冲区安装在内存模块上。缓冲器和存储器控制器通过数据接线，命令/地址接线和时钟接线相互连接。存储器模块中的DRAM和缓冲器通过内部数据接线，内部命令/地址布线和内部旋塞线连接。数据接线，命令/地址接线和时钟接线可以级联连接到其他存储器模块的缓冲器。在DRAM和存储器模块的缓冲器之间，使用与时钟同步的数据相位信号实现高速数据传输。

73. 发明申请

US20080298147A1 Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20080298147A1
公开(公告)日：2008-12-04
申请号：US12149856
申请日：2008-05-09
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/5006
摘要： To arrange data input/output PADs of a semiconductor memory on a narrower pitch without enhancing a required positional accuracy for a probe in a probe check. A semiconductor memory includes: a memory cell array including memory cells; signal terminals; a power source terminal of a power source supplied to output circuits of the signal terminals; test-purpose signal terminals fewer than the signal terminals; a selection portion which, as data to be written to the memory cells, selects data input from the signal terminals or data input from the test-purpose signal terminals, and repetitively allocates inputs of the test-purpose signal terminals to inputs of the signal terminals based on an arrangement of the signal terminals; and a test-purpose power source terminal connected to the power source terminal, and arrangement intervals of the test-purpose signal terminals and the test-purpose power source terminal are larger than an arrangement interval of the signal terminals.
摘要翻译：以较窄的间距布置半导体存储器的数据输入/输出PAD，而不增加探针检查中的探针所需的位置精度。半导体存储器包括：包括存储单元的存储单元阵列; 信号端子; 提供给信号端子的输出电路的电源的电源端子; 测试用信号端子少于信号端子; 选择部分，作为要写入存储单元的数据，选择从信号端子输入的数据或从测试用信号端子输入的数据，并将测试用信号端子的输入重复地分配给信号端子的输入基于信号端子的布置; 连接到电源端子的测试用电源端子，测试用信号端子和测试用电源端子的配置间隔大于信号端子的配置间隔。

74. 发明授权

US07356750B2 Data transmission method and data transmission apparatus 有权
标题翻译：数据传输方法和数据传输装置
公开(公告)号：US07356750B2
公开(公告)日：2008-04-08
申请号：US11518159
申请日：2006-09-11
申请人： Hideaki Fukushima , Seiji Horii , Tatsuya Ohnishi , Makoto Hagai , Yoshinori Matsui , Akihiro Miyazaki
发明人： Hideaki Fukushima , Seiji Horii , Tatsuya Ohnishi , Makoto Hagai , Yoshinori Matsui , Akihiro Miyazaki
IPC分类号： G08C25/02 , H04L1/18 , H04J3/24
CPC分类号： H04L1/1809 , H04L1/008 , H04L1/1642 , H04L1/1838 , H04L1/1854 , H04L1/1877 , H04L1/1887
摘要： A data transmission apparatus including a receiving unit for receiving transmitted packets; a priority decision unit; a retransmission packet storage unit; a retransmission instruction receiving unit for receiving a retransmission request from a terminal at the receiving end; a retransmission decision unit; a transmission queue management unit; and a transmission unit.
摘要翻译：一种数据发送装置，包括：接收发送分组的接收单元; 优先决策单位; 重传分组存储单元; 重发指令接收单元，用于从接收端的终端接收重传请求; 重发决策单元; 传输队列管理单元; 和发送单元。

75. 发明申请

US20080074940A1 Self-refresh timer circuit and method of adjusting self-refresh timer period 失效
标题翻译：自刷新定时器电路及调整自刷新定时器周期的方法
公开(公告)号：US20080074940A1
公开(公告)日：2008-03-27
申请号：US11984352
申请日：2007-11-16
申请人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
发明人： Yoshinori Matsui , Hitoshi Tanaka , Kazuhiko Kajigaya , Akiyoshi Yamamoto , Tadashi Onodera
IPC分类号： G11C7/04
CPC分类号： G11C11/406 , G11C11/40615
摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.
摘要翻译：一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

76. 发明授权

US07345941B2 Semiconductor memory device and method of refreshing the semiconductor memory device 失效
标题翻译：半导体存储器件和刷新半导体存储器件的方法
公开(公告)号：US07345941B2
公开(公告)日：2008-03-18
申请号：US11049732
申请日：2005-02-04
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4065
摘要： When a semiconductor memory device enters a refresh mode, retention times of memory cells are measured for each word line. A plurality of refresh cycles are set in correspondence to the retention times of the memory cells. According to the refresh cycles, the memory cells are refreshed.
摘要翻译：当半导体存储器件进入刷新模式时，对每个字线测量存储器单元的保持时间。对应于存储单元的保持时间设置多个刷新周期。根据刷新周期，刷新存储单元。

77. 发明授权

US07333439B2 Sending/receiving method, and device for the same 有权
标题翻译：发送/接收方法和设备相同
公开(公告)号：US07333439B2
公开(公告)日：2008-02-19
申请号：US10168367
申请日：2001-08-13
申请人： Tomoaki Itoh , Takao Yamaguchi , Junichi Sato , Hiroshi Arakawa , Yoshinori Matsui , Yoji Notoya
发明人： Tomoaki Itoh , Takao Yamaguchi , Junichi Sato , Hiroshi Arakawa , Yoshinori Matsui , Yoji Notoya
IPC分类号： H04J1/16 , H04L12/28
CPC分类号： H04W28/22 , H04L1/0002 , H04L1/1614 , H04L1/1809 , H04L1/1838 , H04L1/1854 , H04L1/203 , H04L43/0829 , H04L47/10 , H04L47/11 , H04L47/14 , H04L47/263 , H04L47/40 , H04L65/608 , H04L2001/0097 , H04L2001/0098 , H04W88/16
摘要： The packet loss in a wired section is reported to a receiving terminal (61) using a loss notification packet from a gateway (62) located at the boundary between a wired section and a wireless section, and thus the causes for packet loss are separated. Also, using this loss notification packet, the packet loss rate in the wired section and the wireless section are separately calculated and the transmission rate and robustness of the data packets are determined with a sending terminal (60) in accordance with the respective loss rate of the sections.
摘要翻译：使用来自位于有线部分和无线部分之间的边界处的网关（62）的丢失通知分组向接收终端（61）报告有线部分中的分组丢失，因此分组丢失的原因被分离。此外，使用该丢失通知包，分别计算有线部分和无线部分中的分组丢失率，并且根据发送终端（60）根据相应的丢失率来确定数据分组的传输速率和鲁棒性部分。

78. 发明授权

US07327590B2 Memory module and memory system 有权
标题翻译：内存模块和内存系统
公开(公告)号：US07327590B2
公开(公告)日：2008-02-05
申请号：US11492981
申请日：2006-07-26
申请人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
发明人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
IPC分类号： G11C5/02
CPC分类号： G11C11/408 , G11C5/00 , G11C5/04 , G11C5/06 , G11C7/1051 , G11C7/1063 , G11C8/12 , G11C29/1201 , G11C29/26 , G11C29/48 , H01L23/5384 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/0401
摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.
摘要翻译：在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传送速率的内部数据信号与系统数据信号，系统数据信号的传输速率受到限制。构成存储器模块的DRAM的电流消耗大，阻碍速度增加。对于该存储器模块，多个DRAM芯片堆叠在IO芯片上。每个DRAM芯片通过贯通电极连接到IO芯片，并且包括用于通过IO芯片相互转换每个DRAM芯片中的系统数据信号和内部数据信号的结构。因此，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。

79. 发明授权

US07293144B2 Cache management controller and method based on a minimum number of cache slots and priority 有权
标题翻译：缓存管理控制器和方法基于最小数量的缓存槽和优先级
公开(公告)号：US07293144B2
公开(公告)日：2007-11-06
申请号：US10968964
申请日：2004-10-21
申请人： Yoshinori Matsui , Katsuhisa Miyata , Nobuyuki Kishi
发明人： Yoshinori Matsui , Katsuhisa Miyata , Nobuyuki Kishi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/121 , G06F12/084 , G06F12/0871 , G06F2212/6042
摘要： In order to solve problems that, when the use area used by data of a certain kind reaches the upper limit value, the cache memory cannot be used even though a space area exists in the use area used by data of other kind and utilization efficiency of the cache memory decreases, and that, when the upper limit value of the use area is discarded, on the other hand, data inside the area held is replaced by other data and disappears, a storage area of a size of a minimum guarantee value corresponding to each computer is set inside a disk cache memory in a control device of a storage device connected to a plurality of computers and a storage area is allocated to each computer in accordance with priority corresponding to each computer.
摘要翻译：为了解决当某种类型的数据使用的使用区域达到上限值时的问题，即使在其他类型的数据使用的使用区域中存在空间区域，也不能使用高速缓冲存储器，并且利用效率高速缓冲存储器减少，并且当使用区域的上限值被丢弃时，另一方面，保持的区域内的数据被其他数据替换并消失，对应于最小保证值的大小的存储区域将每个计算机设置在连接到多个计算机的存储设备的控制设备中的盘缓存存储器内，并且根据与每个计算机对应的优先级将存储区域分配给每个计算机。

80. 发明申请

US20070185941A1 Information recording medium, multiplexer, and decoder 审中-公开
标题翻译：信息记录介质，多路复用器和解码器
公开(公告)号：US20070185941A1
公开(公告)日：2007-08-09
申请号：US10594280
申请日：2005-08-29
申请人： Yoshinori Matsui , Satoshi Kondo , Tomoyuki Okada , Wataru Ikeda , Hiroshi Yahata , Tadamasa Toma
发明人： Yoshinori Matsui , Satoshi Kondo , Tomoyuki Okada , Wataru Ikeda , Hiroshi Yahata , Tadamasa Toma
IPC分类号： G06F17/30
CPC分类号： H04N21/435 , G11B20/12 , H04N21/235 , H04N21/2362
摘要： Provided is a multiplexer which can reliably analyze side information which a decoder in the multiplexer can fundamentally identify. A multiplexer (10a) generates data by assigning different packet identifiers to (i) one of coded video data and coded audio data, and (ii) table data regarding the coded data, and packet-multiplexing the coded data and the table data. The multiplexer (10a) includes: a sub-descriptor generating unit (14) which generates sub-descriptors, each of which includes a sub-tag value representing a type of side information representing a parameter for decoding the coded data, and the side information; a descriptor generating unit (11) which generates a main descriptor including the sub-descriptors generated by the sub-descriptor generating unit (14), and a main tag value representing a set of the sub-descriptors; and a table generating unit (12) which generates the table data, by associating the main descriptor generated by the descriptor generating unit (11), with the packet identifier of the coded data. The sub-descriptor generating unit (11) outputs the sub-descriptors in an order defined by a predetermined storage rule.
摘要翻译：提供了一种可以可靠地分析多路复用器中的解码器可以从根本上识别的副信息的多路复用器。复用器（10a）通过分配不同的分组标识符来生成数据，（i）编码视频数据和编码音频数据中的一个，以及（ii）关于编码数据的表格数据，以及对编码数据和表格数据进行分组复用。多路复用器（10a）包括：子描述符生成单元（14），其生成子描述符，每个子描述符包括表示用于解码编码数据的参数的侧信息的类型的子标签值，信息; 描述符生成单元（11），生成包含由子描述符生成单元（14）生成的子描述符的主描述符，以及表示一组子描述符的主标签值; 以及通过将由描述符生成单元（11）生成的主描述符与编码数据的分组标识符相关联来生成表数据的表生成单元（12）。子描述符生成单元（11）以预定的存储规则定义的顺序输出子描述符。

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