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71. 发明申请

US20110019049A1 PHOTO DETECTING APPARATUS AND UNIT PIXEL THEREOF 有权
标题翻译：照片检测装置及其像素
公开(公告)号：US20110019049A1
公开(公告)日：2011-01-27
申请号：US12844381
申请日：2010-07-27
申请人： Young Gu Jin , Kwan-Young Oh , Samuel Sungmok Lee , Kwang-Chol Choe , Se-Won Seo , Yoon-Dong Park , Eric Fossum , Kyoung-Lae Cho
发明人： Young Gu Jin , Kwan-Young Oh , Samuel Sungmok Lee , Kwang-Chol Choe , Se-Won Seo , Yoon-Dong Park , Eric Fossum , Kyoung-Lae Cho
IPC分类号： H01L27/146 , H04N5/335
CPC分类号： H01L27/14609 , G01S7/4863 , H01L27/14643 , H04N5/335 , H04N5/3741 , H04N5/378
摘要： A unit pixel of a photo detecting apparatus includes a photogate, a transfer gate and a floating diffusion region. The photogate includes a junction gate extending in a first direction and a plurality of finger gates extending from the junction gate in a second direction substantially perpendicular to the first direction. The transfer gate is formed adjacent to the junction gate. The floating diffusion region is formed adjacent to the first transfer gate.
摘要翻译：光检测装置的单位像素包括光栅，传输门和浮动扩散区。光栅包括沿第一方向延伸的接合栅极和从基本上垂直于第一方向的第二方向从接合栅极延伸的多个指状栅极。传输门形成在接合栅极附近。浮动扩散区域形成为与第一传输门相邻。

72. 发明授权

US07842995B2 Multi-bit non-volatile memory devices and methods of fabricating the same 失效
标题翻译：多位非易失性存储器件及其制造方法
公开(公告)号：US07842995B2
公开(公告)日：2010-11-30
申请号：US11523019
申请日：2006-09-19
申请人： Yoon-Dong Park , Won-Joo Kim
发明人： Yoon-Dong Park , Won-Joo Kim
IPC分类号： H01L29/94
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/7851 , H01L29/788 , H01L29/792
摘要： A multi-bit non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins protruding above the body. A first insulation layer may be formed on the body between the at least one pair of fins. A plurality of pairs of control gate electrodes may extend across the first insulation layer and the at least one pair of fins, and may at least partly cover upper portions of outer walls of the at least one pair of fins. A plurality of storage nodes may be formed between the control gate electrodes and the at least one pair of fins, and may be insulated from the substrate. A first distance between adjacent pairs of control gate electrodes may be greater than a second distance between control gate electrodes in each pair.
摘要翻译：多位非易失性存储器件可以包括半导体衬底，其包括主体和突出在主体上方的至少一对鳍。可以在至少一对翅片之间的主体上形成第一绝缘层。多对控制栅电极可以延伸穿过第一绝缘层和至少一对翅片，并且可以至少部分地覆盖至少一对翅片的外壁的上部。多个存储节点可以形成在控制栅极电极和至少一对散热片之间，并且可以与衬底绝缘。相邻的控制栅电极对之间的第一距离可以大于每对控制栅电极之间的第二距离。

73. 发明申请

US20100277622A1 Image sensor including noise removing unit, image pickup device having the image sensor, and image sensing method performed in the image sensor 有权
标题翻译：包括噪声去除单元，具有图像传感器的图像拾取装置和在图像传感器中执行的图像感测方法的图像传感器
公开(公告)号：US20100277622A1
公开(公告)日：2010-11-04
申请号：US12662673
申请日：2010-04-28
申请人： Eric Fossum , Kyoung Lae Cho , Yoon Dong Park , Young Gu Jin , Seung Hoon Lee , Sung-Jae Byun
发明人： Eric Fossum , Kyoung Lae Cho , Yoon Dong Park , Young Gu Jin , Seung Hoon Lee , Sung-Jae Byun
IPC分类号： H04N5/217
CPC分类号： H04N5/3575 , H04N5/378
摘要： An image sensor including a noise removing unit may sense images accurately by measuring the amount of noise generated when the image sensor does not perform a sensing operation, storing information about the measured noise amount in each pixel, and removing photocharge corresponding to the information about the measured noise amount during image sensing.
摘要翻译：包括噪声消除单元的图像传感器可以通过测量当图像传感器不执行感测操作时产生的噪声量，存储关于每个像素中测得的噪声量的信息，并且除去与关于测量图像感测时的噪声量。

74. 发明申请

US20100237312A1 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20100237312A1
公开(公告)日：2010-09-23
申请号：US12659175
申请日：2010-02-26
申请人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
发明人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
IPC分类号： H01L45/00
CPC分类号： H01L27/2445 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147
摘要： The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.
摘要翻译：非易失性存储器件包括至少一对第一电极线，设置在至少一对第一电极线之间的至少一个器件结构和设置在该至少一个器件结构与至少一对第一电极线之间的电介质层电极线。所述至少一个器件结构包括第二电极线，所述第二电极线包括第一导电类型半导体，与所述第二电极线相邻的电阻改变材料层，与所述电阻变化材料层相邻的通道，并且包括不同于所述第一导电类型的第一导电型半导体导电型半导体和与沟道相邻的第三电极线，并且包括第一导电型半导体。

75. 发明授权

US07796432B2 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07796432B2
公开(公告)日：2010-09-14
申请号：US12149213
申请日：2008-04-29
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C2213/71
摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.
摘要翻译：非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。多个NAND串可以在多个半导体层上。多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。公共位线可以在存储器单元的第一端处共同连接到每个NAND串。公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

76. 发明授权

US07791942B2 Methods of operating nonvolatile memory devices 有权
标题翻译：操作非易失性存储设备的方法
公开(公告)号：US07791942B2
公开(公告)日：2010-09-07
申请号：US12073314
申请日：2008-03-04
申请人： Won-joo Kim , Tae-hee Lee , Jae-woong Hyun , Yoon-dong Park
发明人： Won-joo Kim , Tae-hee Lee , Jae-woong Hyun , Yoon-dong Park
IPC分类号： G11C16/04
CPC分类号： G11C16/34
摘要： Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.
摘要翻译：提供了非易失性存储器件的操作方法。在操作包括多个存储单元的非易失性存储器件的方法中，通过在其中记录有记录数据的存储单元的通道上感应升压电压来稳定记录数据。从多个存储单元中选择存储单元，并且所选存储单元的通道上的升压电压由连接到所选存储单元的至少一个存储单元的通道电压引起。

77. 发明申请

US20100177566A1 Non-volatile memory device having stacked structure, and memory card and electronic system including the same 有权
标题翻译：具有堆叠结构的非易失性存储器件，以及包括该堆叠结构的存储卡和电子系统
公开(公告)号：US20100177566A1
公开(公告)日：2010-07-15
申请号：US12656043
申请日：2010-01-14
申请人： Won-joo Kim , Yoon-dong Park , Jung-hun Sung , Yong-koo Kyoung , Sang-moo Choi , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , Jung-hun Sung , Yong-koo Kyoung , Sang-moo Choi , Tae-hee Lee
IPC分类号： G11C16/04
CPC分类号： H01L27/11578 , G11C16/0483 , G11C16/08 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11556
摘要： Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.
摘要翻译：提供了具有堆叠结构的非易失性存储器件，以及存储卡和包括其的系统。非易失性存储器件可以包括衬底。堆叠的NAND单元阵列可以具有至少一个NAND组，并且每个NAND组可以包括垂直堆叠在衬底上的多个NAND串。至少一个信号线可以布置在衬底上，以便与至少一个NAND组共同耦合。

78. 发明申请

US20100141821A1 Image Sensor Devices Having Dual-Gated Charge Storage Regions Therein 有权
标题翻译：具有双门控充电存储区域的图像传感器设备
公开(公告)号：US20100141821A1
公开(公告)日：2010-06-10
申请号：US12632989
申请日：2009-12-08
申请人： Eric R. Fossum , Young Gu Jin , Soo Jung Hwang , Dae Kil Cha , Yoon Dong Park , Jung Chak Ahn , Kyoung Sik Moon
发明人： Eric R. Fossum , Young Gu Jin , Soo Jung Hwang , Dae Kil Cha , Yoon Dong Park , Jung Chak Ahn , Kyoung Sik Moon
IPC分类号： H04N5/335 , H01L31/14
CPC分类号： H01L27/14812 , H01L27/14609 , H01L27/14641 , H01L27/14643 , H04N5/37452
摘要： An image sensor device may include a dual-gated charge storage region within a substrate. The dual-gated charge storage region includes first and second diodes within a common charge generating region. This charge generating region is configured to receive light incident on a surface of the image sensor device. The first and second diodes include respective first conductivity type regions responsive to first and second gate signals, respectively. These first and second gate signals are active during non-overlapping time intervals.
摘要翻译：图像传感器装置可以包括衬底内的双门控电荷存储区域。双门控电荷存储区域包括公共电荷产生区域内的第一和第二二极管。该电荷产生区被配置为接收入射在图像传感器装置的表面上的光。第一和第二二极管分别包括响应于第一和第二栅极信号的相应的第一导电类型区域。这些第一和第二门信号在非重叠时间间隔期间是有效的。

79. 发明授权

US07729175B2 Method of writing/reading data into/from memory cell and page buffer using different codes for writing and reading operations 有权
标题翻译：使用不同的代码进行写入和读取操作，从存储单元和页面缓冲区写入/读取数据的方法
公开(公告)号：US07729175B2
公开(公告)日：2010-06-01
申请号：US12010481
申请日：2008-01-25
申请人： Kyoung-lae Cho , Yoon-dong Park , Jun-jin Kong , Seung-hoon Lee , Jae-woong Hyun , Sung-jae Byun , Ju-hee Park , Seung-hwan Song
发明人： Kyoung-lae Cho , Yoon-dong Park , Jun-jin Kong , Seung-hoon Lee , Jae-woong Hyun , Sung-jae Byun , Ju-hee Park , Seung-hwan Song
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C2211/5642
摘要： Provided are a method of writing/reading data into/from a memory cell and a page buffer using different codes for the writing and reading operations. The method of writing/reading data into/from a memory cell that has a plurality of threshold voltage distributions includes a data writing operation and a data reading operation. In the data writing operation, data having a plurality of bits is written into the memory cell by using a plurality of writing codes corresponding to threshold voltage distributions. In the data reading operation, the data having a plurality of bits is read from the memory cell by using reading codes corresponding to the threshold voltage distributions from among the threshold voltage distributions. In the method of writing/reading data into/from a memory cell, a part of the writing codes is different from a corresponding part of the reading codes.
摘要翻译：提供了一种将数据写入/从存储单元读取数据的方法和使用不同代码进行写入和读取操作的页面缓冲器。对具有多个阈值电压分布的存储单元写入/读取数据的方法包括数据写入操作和数据读取操作。在数据写入操作中，通过使用与阈值电压分布对应的多个写入代码，将具有多个位的数据写入存储单元。在数据读取操作中，通过使用与阈值电压分布中的阈值电压分布相对应的读取代码，从存储单元读取具有多个位的数据。在将数据写入/从存储单元读取的方法中，写入代码的一部分与读取代码的相应部分不同。

80. 发明申请

US20100126584A1 SOLAR CELLS AND SOLAR CELL MODULES 审中-公开
标题翻译：太阳能电池和太阳能电池模块
公开(公告)号：US20100126584A1
公开(公告)日：2010-05-27
申请号：US12619042
申请日：2009-11-16
申请人： Kwang-Soo Seol , Yoon-Dong Park
发明人： Kwang-Soo Seol , Yoon-Dong Park
IPC分类号： H01L31/00
CPC分类号： H01L31/03529 , G02B6/12007 , H01L31/035281 , H01L31/0543 , H01L31/0547 , Y02E10/52
摘要： A solar cell module includes a solar cell provided at a center area of a support to expose an edge area of the support. An optical waveguide layer is provided on the edge area of the support to concentrate light to the solar cell.
摘要翻译：太阳能电池模块包括设置在支撑件的中心区域以暴露支撑件的边缘区域的太阳能电池。在支撑体的边缘区域设置光波导层，以将光聚集到太阳能电池。

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