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71. 发明申请

US20100156486A1 DLL CIRCUIT HAVING ACTIVATION POINTS 有权
标题翻译：具有激活点的DLL电路
公开(公告)号：US20100156486A1
公开(公告)日：2010-06-24
申请号：US12428507
申请日：2009-04-23
申请人： Won Joo YUN , Hyun Woo LEE
发明人： Won Joo YUN , Hyun Woo LEE
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818
摘要： A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.
摘要翻译：延迟锁定环路（DLL）电路包括延迟线，其被配置为通过响应于延迟控制信号延迟参考时钟信号来产生延迟时钟信号，延迟线具有两个或更多个初始激活点，其中初始激活点为根据延迟控制信号的初始值选择; 延迟补偿单元，被配置为通过将所述延迟时钟信号延迟预定时间来产生反馈时钟信号; 相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号; 以及延迟控制单元，被配置为响应于相位检测信号而产生延迟控制信号。

72. 发明申请

US20090322391A1 PHASE SYNCHRONIZATION APPARATUS 有权
标题翻译：相位同步装置
公开(公告)号：US20090322391A1
公开(公告)日：2009-12-31
申请号：US12345149
申请日：2008-12-29
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.
摘要翻译：相位同步装置包括：偏置控制单元，被配置为顺序地延迟输入时钟信号以产生具有多个位的偏置控制信号;偏置生成单元，被配置为产生具有与偏置的逻辑值对应的电平的上拉偏置电压控制信号，并且响应于控制信号产生下拉偏置电压; 以及压控振荡器，被配置为包括分别具有上拉端子和下拉端子的多个延迟单元，以响应于所述控制电压而产生输出时钟信号，其中所述上拉偏置电压被提供给各个延迟单元的上拉端子和下拉偏压被提供给各个延迟单元的下拉端子。

73. 发明授权

US07633324B2 Data output strobe signal generating circuit and semiconductor memory apparatus having the same 有权
标题翻译：数据输出选通信号发生电路及其半导体存储装置
公开(公告)号：US07633324B2
公开(公告)日：2009-12-15
申请号：US11878074
申请日：2007-07-20
申请人： Won-Joo Yun , Hyun-Woo Lee
发明人： Won-Joo Yun , Hyun-Woo Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , H03K5/1565 , H03K2005/00058
摘要： A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected clock and generates a data output strobe signal. A duty cycle control unit receives the data output strobe signal and outputs the control signal.
摘要翻译：数据输出选通信号产生电路包括占空比校正单元，其根据控制信号校正输入时钟的占空比，以产生校正时钟。数据输出选通信号发生单元接收校正的时钟并产生数据输出选通信号。占空比控制单元接收数据输出选通信号并输出控制信号。

74. 发明申请

US20090295446A1 DUTY CYCLE CORRECTING CIRCUIT AND METHOD OF CORRECTING A DUTY CYCLE 有权
标题翻译：占空比校正电路和校正周期的方法
公开(公告)号：US20090295446A1
公开(公告)日：2009-12-03
申请号：US12345480
申请日：2008-12-29
申请人： Won-Joo Yun , Hyun-Woo Lee
发明人： Won-Joo Yun , Hyun-Woo Lee
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correcting circuit includes a duty ratio control unit configured to alternately change logical values of a plurality of bits of a pull-up control signal and a plurality of bits of a pull-down control signal in response to a duty ratio detection signal, a duty ratio correcting unit configured to adjust driving abilities of a first driver and a second driver in response to the plurality of bits of the pull-up control signal and the plurality of bits of the pull-down control signal to output a correction clock signal, and a duty ratio detecting unit configured to detect a duty ratio of the correction clock to generate the duty ratio detection signal.
摘要翻译：占空比校正电路包括占空比控制单元，其被配置为响应于占空比检测信号交替地改变上拉控制信号的多个比特和下拉控制信号的多个比特的逻辑值，占空比校正单元，被配置为响应于所述上拉控制信号的多个比特和所述下拉控制信号的多个比特来调整第一驱动器和第二驱动器的驱动能力，以输出校正时钟信号以及占空比检测单元，被配置为检测校正时钟的占空比以产生占空比检测信号。

75. 发明申请

US20090273382A1 CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE 有权
标题翻译：校正周期的电路和方法
公开(公告)号：US20090273382A1
公开(公告)日：2009-11-05
申请号：US12500007
申请日：2009-07-09
申请人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
发明人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00058 , H03K2005/00221
摘要： A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal.
摘要翻译：配置为校正占空比的电路包括时钟分频单元，被配置为将输入时钟信号延迟指定的延迟量并产生多个延迟时钟信号;时钟选择单元，被配置为输出多个延迟时钟信号作为响应于输入时钟信号的占空比信息的选择的延迟时钟信号;边缘控制单元，被配置为通过控制所选择的延迟时钟信号的下降沿来产生下降时钟信号，并通过控制产生上升时钟信号基于关于输入时钟信号的高持续时间和低持续时间之间的差的信息的输入时钟信号的下降沿，以及用于混合下降时钟信号和上升时钟信号的相位的相位混合单元，并产生输出时钟信号。

76. 发明授权

US07560963B2 Delay-locked loop apparatus and delay-locked method 有权
标题翻译：延迟锁定环路设备和延时锁定方式
公开(公告)号：US07560963B2
公开(公告)日：2009-07-14
申请号：US11683500
申请日：2007-03-08
申请人： Won Joo Yun , Hyun Woo Lee
发明人： Won Joo Yun , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0814 , H03L7/0818 , H03L7/10
摘要： A delay-locked loop device compensates a skew between an external clock and data or between an external clock and an internal clock particularly by applying a single delay model portion, a complementary phase multiplexing, and a cascade delay line. This device performs an operation by selecting any one of an external clock signal (CLK) and an inverted external clock signal (CLKB) using a multiplexing portion 200, aligning the selected clock signal at a rising edge of the external clock signal (CLK) through a first single coarse delay line 212, a first dual coarse delay line 222, and a first fine delay unit 223 according to the phase comparison with a feedback clock signal (FBCLK) through a delay model portion 250, then receiving a clock signal through the first single coarse delay line 212 to the second single coarse delay line 214 to align the rising edges of the rising clock signal (RCLK) and the falling clock signal (FCLK).
摘要翻译：延迟锁定环路装置补偿外部时钟和数据之间或外部时钟与内部时钟之间的偏差，特别是通过应用单个延迟模型部分，互补相位复用和级联延迟线。该装置通过使用多路复用部分200选择外部时钟信号（CLK）和反相外部时钟信号（CLKB）中的任何一个来执行操作，在外部时钟信号（CLK）的上升沿通过根据与延迟模型部分250的反馈时钟信号（FBCLK）的相位比较，第一单个粗略延迟线212，第一双粗略延迟线222和第一精细延迟单元223，然后通过延迟模型部分250接收时钟信号第一单个粗略延迟线212到第二单个粗略延迟线214，以对准上升时钟信号（RCLK）和下降时钟信号（FCLK）的上升沿。

77. 发明申请

US20090146709A1 DELAY CIRCUIT OF DELAY LOCKED LOOP HAVING SINGLE AND DUAL DELAY LINES AND CONTROL METHOD OF THE SAME 有权
标题翻译：具有单双延时线的延迟锁定环的延迟电路及其控制方法
公开(公告)号：US20090146709A1
公开(公告)日：2009-06-11
申请号：US12172887
申请日：2008-07-14
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/08
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00052 , H03K2005/00058
摘要： A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.
摘要翻译：延迟锁定环路中的延迟电路包括：第一延迟电路单元，用于响应于第一控制信号使用单个延迟线延迟输入信号，然后输出第一延迟信号和第二延迟信号;以及第二延迟电路单元，使用双延迟线延迟与第二控制信号和第三控制信号对应的延迟时间的第一延迟信号和第二延迟信号，然后输出第三延迟信号和第四延迟信号。

78. 发明申请

US20090146708A1 DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME 失效
标题翻译： DLL电路及其控制方法
公开(公告)号：US20090146708A1
公开(公告)日：2009-06-11
申请号：US12172137
申请日：2008-07-11
申请人： Won Joo Yun , Hyun Woo Lee
发明人： Won Joo Yun , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0805 , H03L7/0814
摘要： A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output clock signal from the second delay line, thereby outputting a duty ratio correction clock signal.
摘要翻译：延迟锁定环路（DLL）电路包括：第一延迟控制单元，被配置为响应于第一相位检测信号产生第一延迟控制信号，以控制第一延迟线的延迟量并输出第一延迟量信息信号，第二延迟控制单元，被配置为响应于第二相位检测信号产生第二延迟控制信号，以控制第二延迟线的延迟量并输出第二延迟量信息信号，并且控制第二延迟控制信号的延迟量延迟线响应于第一延迟控制信号和半周期信息信号，半周期检测单元被配置为接收第一延迟量信息信号和第二延迟量信息信号以提取参考时钟信号的半周期信息，从而生成半周期信息信号，以及占空比校正单元，被配置为组合来自第一d的输出时钟信号 elay线和来自第二延迟线的输出时钟信号，从而输出占空比校正时钟信号。

79. 发明授权

US07535270B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07535270B2
公开(公告)日：2009-05-19
申请号：US11819783
申请日：2007-06-29
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/07 , H03L7/0814 , H03L7/0818
摘要： A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.
摘要翻译：半导体存储器件包括用于校正延迟锁定时钟信号的占空比的延迟锁定环路。半导体存储器件包括延迟锁定电路，占空比校正电路和时钟同步电路。延迟锁定电路通过将系统时钟延迟预定时间来输出延迟锁定时钟。占空比校正电路通过校正延迟锁定时钟的占空比来输出第一时钟，其中延迟锁定时钟的高电平到低电平周期的比例根据第一时钟的第二边沿和来自第一时钟的第二时钟的信号。时钟同步电路将第一时钟的第一边沿与第二时钟的第一边沿同步。

80. 发明申请

US20080252350A1 CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE 有权
标题翻译：校正周期的电路和方法
公开(公告)号：US20080252350A1
公开(公告)日：2008-10-16
申请号：US11961931
申请日：2007-12-20
申请人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
发明人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K2005/00058 , H03K2005/00221
摘要： A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals.
摘要翻译：用于校正占空比的电路包括占空比数字转换块，被配置为输出作为多位数字信号的输入时钟信号的占空比信息;占空比信息分析块，被配置为分析输入时钟信号的占空比信息产生边沿控制信号，并选择多个延迟时钟信号中的任一个，以及占空比控制块，被配置为响应于边沿控制信号来控制所选择的延迟时钟信号和输入时钟信号的占空比。

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