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71. 发明申请

US20050164446A1 Method for manufacturing single-sided buried strap in semiconductor devices 有权
标题翻译：在半导体器件中制造单面埋入带的方法
公开(公告)号：US20050164446A1
公开(公告)日：2005-07-28
申请号：US10940761
申请日：2004-09-15
申请人： Shian-Jyh Lin , Chia-Sheng Yu
发明人： Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/306 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L21/8244
CPC分类号： H01L27/10867
摘要： A method for manufacturing a single-ended buried strap used in semiconductor devices is disclosed. According to the present invention, a trench capacitor structure is formed in a semiconductor substrate, wherein the trench capacitor structure has a contact surface lower than a surface of the semiconductor substrate such that a recess is formed. Then, an insulative layer is formed on a sidewall of the recess. Next, impurities are implanted into a portion of the insulative layer, and the impurity-containing insulative layer is thereafter removed such that at least a portion of the contact surface and a portion of sidewall of the recess are exposed. A buried strap is sequentially formed on the exposed sidewall of the recess to be in contact with the exposed contact surface.
摘要翻译：公开了一种制造半导体器件中使用的单端掩埋带的方法。根据本发明，在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有比半导体衬底的表面低的接触表面，从而形成凹部。然后，在凹部的侧壁上形成绝缘层。接下来，将杂质注入到绝缘层的一部分中，然后去除含杂质的绝缘层，使得接触表面的至少一部分和凹部的侧壁的一部分露出。在凹部的暴露的侧壁上依次形成埋设的带子，以与暴露的接触表面接触。

72. 发明授权

US09024377B2 Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof 有权
标题翻译：能够减少相邻字线或相邻晶体管的影响的半导体器件及其制造方法
公开(公告)号：US09024377B2
公开(公告)日：2015-05-05
申请号：US13325063
申请日：2011-12-14
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L27/108
CPC分类号： H01L29/792 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
摘要翻译：本发明提供能够减少相邻字线的影响的半导体装置。半导体器件包括：衬底和设置在衬底中的字线。字线包括：栅电极，设置在栅极电极和衬底之间的栅介质层和邻近栅电极设置的至少一个第一电荷俘获电介质层，其中第一电荷俘获电介质层包括HfO 2，TiO 2，ZrO 2 锗纳米晶层，有机电荷俘获材料，HfSiOxNy或MoSiOqNz。

73. 发明申请

US20130299884A1 MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE 审中-公开
标题翻译：用于制造存储器件的存储器件和方法
公开(公告)号：US20130299884A1
公开(公告)日：2013-11-14
申请号：US13468797
申请日：2012-05-10
申请人： Shian Jyh Lin , Jen Jui Huang
发明人： Shian Jyh Lin , Jen Jui Huang
IPC分类号： H01L29/772 , H01L21/02
CPC分类号： H01L21/76224 , H01L27/10876 , H01L27/10891
摘要： A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area having source and drain regions. The first and second trench isolations extend parallel to each other. The line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area and is formed in the substrate adjacent to the first trench isolation defining a first segment of the active area with the first trench isolation. The second word line extends across the active area and is formed in the substrate adjacent to the second trench isolation defining a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.
摘要翻译：存储器件包括衬底，第一和第二沟槽隔离，多个线型隔离，第一字线和第二字线。衬底包括具有源区和漏区的有源区。第一和第二沟槽隔离物彼此平行延伸。线型隔离定义了有源区以及第一和第二沟槽隔离。第一字线延伸穿过有效区域，并且形成在邻近第一沟槽隔离物的衬底中，限定具有第一沟槽隔离的有源区域的第一段。第二字线延伸穿过有效区域并且形成在与第二沟槽隔离件相邻的衬底中，限定具有第二沟槽隔离的有源区域的第二段。第一段的大小基本上等于第二段的大小。

74. 发明授权

US08044449B2 Memory device with a length-controllable channel 有权
标题翻译：具有长度可控通道的存储器
公开(公告)号：US08044449B2
公开(公告)日：2011-10-25
申请号：US12183021
申请日：2008-07-30
申请人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
发明人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.
摘要翻译：提供存储器件。存储器件包括衬底，具有形成在衬底中的上部和下部的沟槽，形成在沟槽的下部的沟槽电容器，形成在沟槽电容器的侧壁上并且远离衬底的顶表面，形成在衬底中用作源极/漏极的沟槽的上部侧的第一掺杂区域，形成在沟槽中并电连接到第一掺杂区域的导电层，顶部形成在导电层上的电介质层，形成在顶部电介质层上的栅极，形成在栅极两侧和衬底上的外延层，以及形成在外延层的顶部上用作源极/漏极的第二掺杂区域。

75. 发明申请

US20110079836A1 DRAM CELL WITH DOUBLE-GATE FIN-FET, DRAM CELL ARRAY AND FABRICATION METHOD THEREOF 有权
标题翻译：具有双栅极熔池的DRAM单元，DRAM单元阵列及其制造方法
公开(公告)号：US20110079836A1
公开(公告)日：2011-04-07
申请号：US12571443
申请日：2009-10-01
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10826 , H01L27/10876 , H01L27/10891
摘要： A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semiconductor substrate. A trench fill dielectric region is inlaid into the top surface of the semiconductor substrate. Two source/drain regions are formed into the top surface of the semiconductor substrate and are sandwiched about the trench fill region. A buried gate electrode is embedded in the lower sidewall recess. A gate dielectric layer is formed on surface of the lower sidewall recess between the semiconductor substrate and the buried gate electrode.
摘要翻译：晶体管结构包括具有顶表面和从顶表面向下延伸的侧壁的半导体衬底，其中每个侧壁包括横向蚀刻到半导体衬底中的垂直上侧壁表面和下侧壁凹槽。将沟槽填充电介质区域嵌入到半导体衬底的顶表面中。两个源极/漏极区域形成在半导体衬底的顶表面中并且夹在沟槽填充区域周围。掩埋栅电极嵌入在下侧壁凹槽中。在半导体衬底和掩埋栅电极之间的下侧壁凹槽的表面上形成栅极电介质层。

76. 发明授权

US07803701B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07803701B2
公开(公告)日：2010-09-28
申请号：US11964516
申请日：2007-12-26
申请人： Shian-Jyh Lin , Shun-Fu Chen , Tse-Chuan Kuo , An-Hsiung Liu
发明人： Shian-Jyh Lin , Shun-Fu Chen , Tse-Chuan Kuo , An-Hsiung Liu
IPC分类号： H01L21/8242 , H01L21/425
CPC分类号： H01L29/945 , H01L23/544 , H01L27/1087 , H01L29/66181 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.
摘要翻译：一种制造半导体器件的方法包括提供具有器件区域和测试键区域的半导体衬底。在器件区域中形成第一沟槽，并且在测试键区域中形成第二沟槽。在第一和第二沟槽中形成具有第一蚀刻选择性的导电层。在第一方向上执行第一注入工艺以在导电层中同时并分别在器件区域和测试键区中形成具有第一杂质和未掺杂区的第一掺杂区。在第二沟槽中执行第二注入工艺以在导电层中形成具有第二杂质的第二掺杂区，其中第二沟槽中的导电层具有高于第一蚀刻选择性的第二蚀刻选择性。

77. 发明授权

US07795090B2 Electrical device and method for fabricating the same 有权
标题翻译：电气装置及其制造方法
公开(公告)号：US07795090B2
公开(公告)日：2010-09-14
申请号：US12211815
申请日：2008-09-17
申请人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
IPC分类号： H01L21/8242
CPC分类号： H01L29/66553 , H01L21/26586 , H01L27/10876 , H01L29/66621 , H01L29/66659
摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
摘要翻译：公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。多个沟槽嵌入在半导体衬底的存储器阵列区域中。每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

78. 发明授权

US07679137B2 Method for fabricating recessed gate MOS transistor device 有权
标题翻译：凹陷栅极MOS晶体管器件的制造方法
公开(公告)号：US07679137B2
公开(公告)日：2010-03-16
申请号：US11696163
申请日：2007-04-03
申请人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
发明人： Pei-Ing Lee , Chien-Li Cheng , Shian-Jyh Lin
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L27/10861 , H01L27/0629 , H01L27/10876
摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

79. 发明授权

US07588984B2 Method to define a transistor gate of a DRAM and the transistor gate using same 有权
标题翻译：使用其定义DRAM的晶体管栅极和晶体管栅极的方法
公开(公告)号：US07588984B2
公开(公告)日：2009-09-15
申请号：US11431588
申请日：2006-05-11
申请人： Yu-Pi Lee , Shian-Jyh Lin
发明人： Yu-Pi Lee , Shian-Jyh Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L27/10838 , H01L27/10876 , H01L27/10891
摘要： A method to determine the predetermined location of a transistor gate of a dynamic random access memory (DRAM). A trench capacitor is respectively provided in a silicon substrate at the two sides of the gate, along the direction of a bit line. The method is to first form a patterned layer of silicon nitride over the substrate so that at the location where the two trench capacitors are desired to be built, the substrate is exposed; then to build the two trench capacitors at the location of the exposed substrate. Form a layer of silicon oxide to cover the capacitors and make the layer of silicon oxide and the layer of silicon nitride at the same level. Layer of silicon nitride is removed afterwards, and a polysilicon layer is conformably formed on the substrate. A BF2 ion implantation is performed twice at different tilt angles on the polysilicon layer in order to define an undoped area between the two trench capacitors. Then remove the undoped area of the polysilicon layer so that part of the silicon substrate is exposed to serve as the predetermined location of transistor gate.
摘要翻译：确定动态随机存取存储器（DRAM）的晶体管栅极的预定位置的方法。沟槽电容器沿着位线的方向在栅极的两侧分别设置在硅衬底中。该方法是首先在衬底上形成图案化的氮化硅层，使得在需要构建两个沟槽电容器的位置处，衬底被暴露; 然后在暴露的基板的位置处构建两个沟槽电容器。形成一层氧化硅以覆盖电容器，并使氧化硅层和氮化硅层处于同一水平。之后去除氮化硅层，并且在衬底上顺应地形成多晶硅层。在多晶硅层上以不同的倾斜角进行两次BF2离子注入，以便限定两个沟槽电容器之间的未掺杂区域。然后去除多晶硅层的未掺杂区域，使得硅衬底的一部分暴露以用作晶体管栅极的预定位置。

80. 发明授权

US07579234B2 Method for fabricating memory device with recess channel MOS transistor 有权
标题翻译：用于制造具有凹槽MOS晶体管的存储器件的方法
公开(公告)号：US07579234B2
公开(公告)日：2009-08-25
申请号：US11960711
申请日：2007-12-20
申请人： Shian-Jyh Lin
发明人： Shian-Jyh Lin
IPC分类号： H01L21/8242
CPC分类号： H01L27/10823 , H01L27/10829 , H01L27/10861 , H01L27/10876
摘要： A method for fabricating line type recess channel MOS transistors utilizes a lithography process to form line type gate trenches in the line type recess channel MOS transistors before finishing a STI process. The method can further control the critical dimension variation in a range required in precision semiconductor processes. Therefore, the short problem between the transistors can be avoided.
摘要翻译：用于制造线型凹槽MOS晶体管的方法利用光刻工艺在完成STI工艺之前在线型凹槽MOS晶体管中形成线型栅极沟槽。该方法可以进一步控制精密半导体工艺所需范围内的临界尺寸变化。因此，可以避免晶体管之间的短暂问题。

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