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71. 发明申请

US20160064083A1 NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译：非易失性存储器件及其编程方法
公开(公告)号：US20160064083A1
公开(公告)日：2016-03-03
申请号：US14733239
申请日：2015-06-08
申请人： SANG-WAN NAM , WANDONG KIM
发明人： SANG-WAN NAM , WANDONG KIM
IPC分类号： G11C16/10 , G11C16/24 , G11C16/08
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/24
摘要： A nonvolatile memory device of the inventive concept includes a memory cell array, an address decoder, a read & write circuit and control logic. The memory cell array includes a plurality of memory blocks including a plurality of cell strings, each cell string including a plurality of memory cells stacked in a direction perpendicular to a substrate. The control logic controls operations so that in a program operation, when the selected word line satisfies a precharge condition, a program voltage to be applied to the selected word line is applied before a pass voltage to be applied to an unselected word line.
摘要翻译：本发明构思的非易失性存储器件包括存储单元阵列，地址解码器，读写电路和控制逻辑。存储单元阵列包括包括多个单元串的多个存储块，每个单元串包括沿垂直于基板的方向堆叠的多个存储单元。控制逻辑控制操作，使得在程序操作中，当所选择的字线满足预充电条件时，在施加到未选字线的通过电压之前施加要施加到所选字线的编程电压。

72. 发明授权

US09076516B2 Method for programming a nonvolatile memory device 有权
标题翻译：非易失性存储器件编程方法
公开(公告)号：US09076516B2
公开(公告)日：2015-07-07
申请号：US13661021
申请日：2012-10-25
申请人： Sang-Wan Nam , Junghoon Park
发明人： Sang-Wan Nam , Junghoon Park
IPC分类号： G11C16/04 , G11C13/00 , G11C16/10 , G11C11/56 , G11C16/34
CPC分类号： G11C13/0002 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648 , G11C2213/71
摘要： Provided is a method for programming a nonvolatile memory device, which includes memory cells arranged in a plurality of rows. The programming method includes alternately selecting word lines to program data at a first page portion and a second page portion associated with the memory cells. After the first and second page portions are programmed, the method includes programming data at a third page portion associated with the memory cells according to an order in which word lines are arranged. The word lines may be sequentially selected one by one from a word line adjacent to a ground selection line.
摘要翻译：提供了一种用于编程非易失性存储器件的方法，其包括以多行布置的存储器单元。编程方法包括交替地选择字线以在与存储器单元相关联的第一页部分处编程数据和第二页面部分。在第一和第二页面部分被编程之后，该方法包括根据排列字线的顺序在与存储器单元相关联的第三页部分处编程数据。字线可以从与地选择线相邻的字线逐个地依次选择。

73. 发明授权

US09036425B2 Memory devices for reducing boosting charge leakage and systems including the same 有权
标题翻译：用于减少增加电荷泄漏的存储器件及包括其的系统
公开(公告)号：US09036425B2
公开(公告)日：2015-05-19
申请号：US13229107
申请日：2011-09-09
申请人： Chi Weon Yoon , Sang-Wan Nam , Dong Hyuk Chae
发明人： Chi Weon Yoon , Sang-Wan Nam , Dong Hyuk Chae
IPC分类号： G11C16/06 , G11C16/04 , G11C16/34
CPC分类号： G11C16/0483 , G11C16/3418
摘要： A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.
摘要翻译：三维（3D）非易失性存储器包括存储单元阵列和合并驱动器，其被配置为将相同电平的合并电压施加到存储单元阵列中的公共源线和体。

74. 发明授权

US08976591B2 Nonvolatile memory device and memory system including the same 有权
标题翻译：非易失性存储器件和包括其的存储器系统
公开(公告)号：US08976591B2
公开(公告)日：2015-03-10
申请号：US13619118
申请日：2012-09-14
申请人： Sang-Wan Nam , Kyung-Hwa Kang , Junghoon Park
发明人： Sang-Wan Nam , Kyung-Hwa Kang , Junghoon Park
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11582
摘要： According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.
摘要翻译：根据示例性实施例，非易失性存储器件包括第一和第二NAND串。第一NAND串包括第一串选择晶体管，第一局部地和第一全局接地选择晶体管，以及沿垂直于衬底的方向堆叠的第一存储单元。第二NAND串包括第二串选择晶体管，第二局部地和第二全局接地选择晶体管，以及沿与基板垂直的方向堆叠的第二存储单元。该器件包括选择线驱动器，其包括被配置为选择并向第一和第二串选择晶体管，第一和第二局部和全局地选择晶体管提供至少一个操作电压的路径晶体管。第一和第二串选择晶体管彼此电绝缘，并且第一和第二全局接地选择晶体管电连接。

75. 发明授权

US08971114B2 Nonvolatile memory devices and driving methods thereof 有权
标题翻译：非易失性存储器件及其驱动方法
公开(公告)号：US08971114B2
公开(公告)日：2015-03-03
申请号：US13368769
申请日：2012-02-08
申请人： Kyung-Hwa Kang , Sang-Wan Nam , Donghyuk Chae , ChiWeon Yoon
发明人： Kyung-Hwa Kang , Sang-Wan Nam , Donghyuk Chae , ChiWeon Yoon
IPC分类号： G11C16/04 , G11C16/08 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/0466 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.
摘要翻译：非易失性存储器件包括具有连接在衬底和多个位线之间并由选择线选择的多个单元串的存储单元阵列，以及配置成在至少两个方向上驱动选择线的选通电路。

76. 发明申请

US20140233316A1 MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF 有权
标题翻译：记忆系统及其编程方法
公开(公告)号：US20140233316A1
公开(公告)日：2014-08-21
申请号：US14060633
申请日：2013-10-23
申请人： Sang-Won Shim , Sang-Wan Nam , Kitae Park
发明人： Sang-Won Shim , Sang-Wan Nam , Kitae Park
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/26 , G11C16/3427 , G11C16/3459
摘要： A program method of a nonvolatile memory device is provided, which includes programming a memory cell in one string selected from a plurality of vertical strings; determining whether a mode of operation of the nonvolatile memory device is a pre-pulse mode; when the mode of operation is determined to be the pre-pulse mode, applying a pre-pulse having a predetermined level to a string selection line connected with a gate of a string selection transistor of at least one unselected vertical string of the plurality of vertical strings for a particular time period; and performing a verification operation on the programmed memory cell.
摘要翻译：提供了一种非易失性存储器件的编程方法，其包括以多个垂直字符串中选择的一个串中的存储器单元进行编程; 确定所述非易失存储器件的工作模式是否是预脉冲模式; 当操作模式被确定为预脉冲模式时，将具有预定电平的预脉冲施加到与多个垂直线中的至少一个未选择垂直弦的串选择晶体管的栅极连接的串选择线特定时间段的字符串; 以及对所编程的存储单元执行验证操作。

77. 发明申请

US20130250677A1 NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND PROGRAM METHOD OF THE SAME 有权
标题翻译：非易失性存储器件，非易失性存储器系统及其程序方法
公开(公告)号：US20130250677A1
公开(公告)日：2013-09-26
申请号：US13661021
申请日：2012-10-25
申请人： Sang-Wan NAM , Junghoon PARK
发明人： Sang-Wan NAM , Junghoon PARK
IPC分类号： G11C16/10
CPC分类号： G11C13/0002 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648 , G11C2213/71
摘要： Disclosed is a method for programming a nonvolatile memory device, which includes memory cells arranged in a plurality of rows. The programming method includes alternately selecting word lines to program data at a first page portion and a second page portion associated with the memory cells. After the first and second page portions are programmed, the method includes programming data at a third page portion associated with the memory cells according to an order in which word lines are arranged. The word lines may be sequentially selected one by one from a word line adjacent to a ground selection line.
摘要翻译：公开了一种用于编程非易失性存储器件的方法，其包括以多行排列的存储器单元。编程方法包括交替地选择字线以在与存储器单元相关联的第一页部分处编程数据和第二页面部分。在第一和第二页面部分被编程之后，该方法包括根据排列字线的顺序在与存储器单元相关联的第三页部分处编程数据。字线可以从与地选择线相邻的字线逐个地依次选择。

78. 发明申请

US20130188423A1 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失性存储器件和包括其的存储器系统
公开(公告)号：US20130188423A1
公开(公告)日：2013-07-25
申请号：US13620002
申请日：2012-09-14
申请人： Sang-Wan NAM
发明人： Sang-Wan NAM
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/04 , G11C16/24 , H01L27/1157 , H01L27/11582
摘要： According to example embodiments of inventive concepts, a nonvolatile memory device includes a first NAND string and a second NAND string. The first NAND string include a first string selection transistor, a first ground selection transistor having a threshold voltage higher than a threshold voltage of the first string selection transistor, and first memory cells stacked on a substrate. The a second NAND string includes a second string selection transistor, a second ground selection transistor having a threshold voltage higher than a threshold voltage of the second string selection transistor, and second memory cells stacked on the substrate. A first selection line may connect the first string selection line and the first ground selection line, and a second selection line may connect the second selection line and the second ground selection line. The first and second selection lines may be electrically isolated from each other.
摘要翻译：根据本发明构思的示例实施例，非易失性存储器件包括第一NAND串和第二NAND串。第一NAND串包括第一串选择晶体管，具有高于第一串选择晶体管的阈值电压的阈值电压的第一接地选择晶体管和堆叠在基板上的第一存储单元。第二NAND串包括第二串选择晶体管，具有高于第二串选择晶体管的阈值电压的阈值电压的第二接地选择晶体管，以及堆叠在基板上的第二存储单元。第一选择线可以连接第一串选择线和第一接地选择线，并且第二选择线可以连接第二选择线和第二接地选择线。第一选择线和第二选择线可以彼此电隔离。

79. 发明申请

US20120047321A1 Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays 审中-公开
标题翻译：用于具有三维存储器单元阵列的非易失性存储器件的地址调度方法
公开(公告)号：US20120047321A1
公开(公告)日：2012-02-23
申请号：US13213806
申请日：2011-08-19
申请人： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
发明人： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0646 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
摘要翻译：至少一个地址调度方法包括选择第一位线，选择连接到第一位线的第一串，在第一串中的每个多电平单元的N页上从底部字线到顶部执行地址调度字线，并且在完成第一串中的所有字线上的地址调度之后，以与对第一字符串执行的相同的方式依次执行第二至第K个字符串的地址调度，其中“k”为2或自然数大于2。

80. 发明申请

US20120039130A1 Nonvolatile Memory Devices, Channel Boosting Methods Thereof, Programming Methods Thereof, And Memory Systems Including The Same 有权
标题翻译：非易失性存储器件，其通道升压方法，其编程方法和包括其的存储器系统
公开(公告)号：US20120039130A1
公开(公告)日：2012-02-16
申请号：US13152776
申请日：2011-06-03
申请人： ChiWeon Yoon , Donghyuk Chae , Sang-Wan Nam , Sung-Won Yun
发明人： ChiWeon Yoon , Donghyuk Chae , Sang-Wan Nam , Sung-Won Yun
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.
摘要翻译：非易失性存储器件通道升压方法，其中至少两个串连接到一个位线，所述通道升压方法包括将初始通道电压施加到所选存储器块中的串的通道，每个具有未编程的浮动禁止串字符串之间的单元格，以及浮动禁止字符串的增强通道。

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