专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20150137204A1 MEMORY CIRCUIT STRUCTURE AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME 有权
标题翻译：存储器电路结构和半导体制造方法
公开(公告)号：US20150137204A1
公开(公告)日：2015-05-21
申请号：US14280688
申请日：2014-05-19
申请人： Powerchip Technology Corporation
发明人： Zih-Song Wang , Chia-Ming Wu
IPC分类号： H01L21/306 , H01L27/115 , H01L21/027
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/32139 , H01L27/11524 , H01L27/1157 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor process for manufacturing particular patterns includes the steps of forming a target layer and evenly-spaced core bodies on a substrate, conformally forming a hard mask layer, forming a first photoresist covering a predetermined region on the hard mask layer wherein the predetermined region encompasses at least two core bodies, performing a first etch process to remove a portion of the hard mask layer outside the predetermined region and expose a number of core bodies, removing the exposed core bodies, forming a second photoresist at least encompassing all the recesses in the predetermined region, and performing a second etch process to pattern the target layer.
摘要翻译：用于制造特定图案的半导体工艺包括以下步骤：在基底上形成目标层和均匀间隔的芯体，保形地形成硬掩模层，形成覆盖硬掩模层上的预定区域的第一光致抗蚀剂，其中预定区域包围至少两个芯体，执行第一蚀刻工艺以去除所述预定区域外的所述硬掩模层的一部分，并暴露多个芯体，去除所述暴露的芯体，形成第二光致抗蚀剂，至少包围所述凹部并且执行第二蚀刻工艺以对目标层进行图案化。

72. 发明授权

US08999809B2 Method for fabricating resistive random access memory 有权
标题翻译：制造电阻随机存取存储器的方法
公开(公告)号：US08999809B2
公开(公告)日：2015-04-07
申请号：US14541159
申请日：2014-11-14
申请人： Powerchip Technology Corporation
发明人： Chan-Ching Lin , Chen-Hao Huang , Tzung-Bin Huang , Chun-Cheng Chen , Ching-Hua Chen
IPC分类号： H01L45/02 , H01L21/02 , H01L45/00 , H01L27/24 , H01L29/66
CPC分类号： H01L45/1608 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/72 , H01L27/2418 , H01L27/2463 , H01L29/6609 , H01L45/04 , H01L45/1226 , H01L45/1253 , H01L45/146 , H01L45/1691
摘要： A method of fabricating a resistive random access memory (RRAM) device is disclosed. A plurality of word lines extending along a first direction are formed on a substrate with a recess between the word lines. A spacer-type resistance layer and a top electrode layer are formed on a sidewall of each of the word lines. A photoresist stripe pattern extending along a second direction is then formed on the substrate. The first direction is perpendicular to the second direction. An etching process is performed to remove the top electrode layer and the spacer-type resistance layer not covered by the photoresist stripe pattern to form a plurality of top electrodes. A diode is formed on each of the top electrodes.
摘要翻译：公开了一种制造电阻随机存取存储器（RRAM）装置的方法。沿着第一方向延伸的多个字线形成在具有在字线之间的凹部的基板上。在每个字线的侧壁上形成间隔型电阻层和顶电极层。然后在基板上形成沿着第二方向延伸的光致抗蚀剂条纹图案。第一方向垂直于第二方向。进行蚀刻处理以去除未被光致抗蚀剂条纹图案覆盖的顶部电极层和间隔物型电阻层，以形成多个顶部电极。在每个顶电极上形成二极管。

73. 发明授权

US08754703B2 Internal voltage trimming circuit, method thereof and semiconductor circuit device comprising the same 有权
标题翻译：内部电压调整电路，其方法和包括该电压调制电路的半导体电路装置
公开(公告)号：US08754703B2
公开(公告)日：2014-06-17
申请号：US13668866
申请日：2012-11-05
申请人： Powerchip Technology Corporation
发明人： Akira Ogawa
IPC分类号： G11C5/14
CPC分类号： G11C29/021 , G11C16/30 , G11C29/028
摘要： TASK: to provide an internal voltage trimming circuit having a simple configuration and operated by a consumption current smaller than that using a comparator. MEANS FOR SOLVING THE PROBLEM: An internal voltage trimming circuit comprises a trimming controller using a change in a counting value of a clock according to a current flowing through a transistor of a power supply current source for a clock generator to trim an internal voltage generated by an internal voltage generator. The trimming controller counts a first counting value of the clock when a predetermined reference voltage is applied to a control terminal of the transistor and a second counting value of the clock when the internal voltage is applied to the control terminal of the transistor and controls the internal voltage generated by the internal voltage generator to substantially coincide the second counting value with the first counting value.
摘要翻译：任务：提供具有简单配置并由比使用比较器的消耗电流更小的消耗电流来操作的内部电压调整电路。解决问题的手段：内部电压调整电路包括微调控制器，该微调控制器使用根据流过时钟发生器的电源电流源的晶体管的电流来改变时钟的计数值，以修整由时钟发生器产生的内部电压内部电压发生器。当将预定的参考电压施加到晶体管的控制端子时，修整控制器对时钟的第一计数值进行计数，并且当内部电压施加到晶体管的控制端子时控制时钟的第二计数值，并且控制内部由内部电压发生器产生的电压基本上与第一计数值重合第二计数值。

74. 发明申请

US20140091273A1 RESISTIVE RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF 有权
标题翻译：电阻随机存取存储器及其制造方法
公开(公告)号：US20140091273A1
公开(公告)日：2014-04-03
申请号：US13674967
申请日：2012-11-13
申请人： POWERCHIP TECHNOLOGY CORPORATION
发明人： Chan-Ching Lin , Chen-Hao Huang , Tzung-Bin Huang , Chun-Cheng Chen , Ching-Hua Chen
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/1608 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/72 , H01L27/2418 , H01L27/2463 , H01L29/6609 , H01L45/04 , H01L45/1226 , H01L45/1253 , H01L45/146 , H01L45/1691
摘要： A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.
摘要翻译：电阻随机存取存储器（RRAM）单元包括沿着第一方向延伸的至少一个位线，设置在衬底上并沿着第二方向延伸以与位线相交的至少一个字线，字线，用于将字线与位线隔离，字线侧壁上的第一存储单元，以及字线另一侧壁上的第二存储单元。

75. 发明授权

US08536008B2 Manufacturing method of vertical channel transistor array 有权
标题翻译：垂直沟道晶体管阵列的制造方法
公开(公告)号：US08536008B2
公开(公告)日：2013-09-17
申请号：US13745867
申请日：2013-01-21
申请人： Powerchip Technology Corporation
发明人： Heiji Kobayashi , Yukihiro Nagai
IPC分类号： H01L21/336
CPC分类号： H01L21/762 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L27/10894
摘要： A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
摘要翻译：垂直沟道晶体管阵列具有由多个半导体柱形成的有源区。多个嵌入式位线平行布置在半导体衬底中并沿列方向延伸。多个位线触点分别设置在一个嵌入位线的一侧。多个嵌入字线平行地布置在嵌入式位线上方并沿行方向延伸。此外，嵌入字线将同一行中的半导体柱与夹在嵌入字线和半导体柱之间的栅介质层连接。电流泄漏隔离结构设置在嵌入式位线的端子处，以防止相邻位线触点之间的电流泄漏。

76. 发明授权

US08470671B1 Method of manufacturing a 3-D vertical memory 有权
标题翻译：三维垂直记忆的制造方法
公开(公告)号：US08470671B1
公开(公告)日：2013-06-25
申请号：US13658816
申请日：2012-10-24
申请人： Powerchip Technology Corporation
发明人： Chao-Wei Lin , Hui-Huang Chen , Chih-Yuan Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7926 , H01L27/11582
摘要： A novel method for manufacturing a 3-D vertical memory comprising the steps of dividing a multilayer structure composed of insulating intermediate layers and sacrificial intermediate layers into a first multilayer structure and a second multilayer structure, replacing the sacrificial intermediate layers in the multilayer structures with metal intermediate layers, and manufacturing the channel structure in two multilayer structures.
摘要翻译：一种用于制造3-D垂直存储器的新方法，包括以下步骤：将由绝缘中间层和牺牲中间层构成的多层结构分成第一多层结构和第二多层结构，用金属代替多层结构中的牺牲中间层中间层，并在两个多层结构中制造通道结构。

77. 发明申请

US20200251480A1 MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20200251480A1
公开(公告)日：2020-08-06
申请号：US16364207
申请日：2019-03-26
申请人： Powerchip Technology Corporation
发明人： Wen-Yueh Jang
IPC分类号： H01L27/11521 , H01L27/11519 , H01L27/11558 , H01L29/788
摘要： A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.

78. 发明申请

US20200235220A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20200235220A1
公开(公告)日：2020-07-23
申请号：US16364210
申请日：2019-03-26
申请人： Powerchip Technology Corporation
发明人： Hung-Kwei Liao , Chen-Chiang Liu , Kuo-Sheng Shih , Yung-Yao Shih , Ming-Tsung Hsu
IPC分类号： H01L29/51 , H01L27/11524 , H01L29/417 , H01L29/40 , H01L21/768
摘要： A manufacturing method of a semiconductor device includes forming a plurality of flash memory structures on a semiconductor substrate, wherein each of the flash memory structures includes a floating gate formed on the semiconductor substrate and a control gate formed on the floating gate; forming at least one pseudo contact between the plurality of flash memory structures; forming a liner film conformally on a surface of the pseudo contact; forming an interlayer dielectric layer on the whole semiconductor substrate to cover the pseudo contact and form at least one air gap between the pseudo contact and the flash memory structure; planarizing the interlayer dielectric layer until the top of the pseudo contact is exposed; removing the pseudo contact to form a contact opening; and forming a conductive material in the contact opening.

79. 发明申请

US20180286877A1 NON-VOLATILE MEMORY STRUCTURE AND METHOD FOR PREVENTING NON-VOLATILE MEMORY STRUCTURE FROM GENERATING PROGRAM DISTURBANCE 审中-公开
公开(公告)号：US20180286877A1
公开(公告)日：2018-10-04
申请号：US15622082
申请日：2017-06-14
申请人： Powerchip Technology Corporation
发明人： Chen-Liang Ma , Zih-Song Wang
IPC分类号： H01L27/11529 , H01L27/1157
CPC分类号： H01L27/11529 , H01L27/1157
摘要： A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.

80. 发明申请

US20180040651A1 IMAGE SENSOR AND RELATED FABRICATION METHOD 有权
公开(公告)号：US20180040651A1
公开(公告)日：2018-02-08
申请号：US15334309
申请日：2016-10-26
申请人： Powerchip Technology Corporation
发明人： Shih-Ping Lee , Yu-An Chen , Hsiu-Wen Huang , Chuan-Hua Chang
IPC分类号： H01L27/146
CPC分类号： H01L27/1461 , H01L27/14625 , H01L27/14645 , H01L27/14685 , H01L27/14689
摘要： An image sensor includes a semiconductor substrate with at least one recess disposed on its surface and in the photosensitive area defined on the surface of the semiconductor substrate, a first-conductivity-type doped region disposed in the semiconductor substrate and in the photosensitive area, and a second-conductivity-type doped region disposed on the surface of the first-conductivity-type doped region and on the surface of the recess. A photosensitive device of the image sensor is formed of the first-conductivity-type doped region and the second-conductivity-type doped region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式