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71. 发明申请

US20100097862A1 FLASH MEMORY DEVICES WITH MEMORY CELLS STRINGS INCLUDING DUMMY TRANSISTORS WITH SELECTIVE THRESHOLD VOLTAGES 有权
标题翻译：具有存储器电池的闪存存储器件包括具有选择性阈值电压的DUMMY TRANSISTORS
公开(公告)号：US20100097862A1
公开(公告)日：2010-04-22
申请号：US12580949
申请日：2009-10-16
申请人： Myoung Gon Kang , Kitae Park
发明人： Myoung Gon Kang , Kitae Park
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/24 , G11C16/3427 , H01L27/11521 , H01L27/11524
摘要： Flash memory devices include a first memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to a bit line and a second memory cell string including a plurality of serially-connected memory cells and first and second serially-connected dummy transistors configured to couple the serially-connected memory cells to the bit line. The first dummy memory cells of the first and second memory cell strings have gates connected in common to a first dummy word line and have different threshold voltages and the second dummy memory cells of the first and second memory cell strings have gates connected in common to a second dummy bit line and have different threshold voltages. In some embodiments, the first dummy memory cell of the first memory cell string and the second dummy memory cell of the second memory cell string may have threshold voltages greater than a predetermined voltage and the second dummy memory cell of the first memory cell string and the first dummy memory cell of the second memory cell string may have threshold voltages less than the predetermined voltage.
摘要翻译：闪速存储器件包括包括多个串联存储器单元的第一存储器单元串和被配置为将串联连接的存储单元耦合到位线的第一和第二串联虚拟晶体管，以及包括多个串联连接的存储器单元和被配置为将串联连接的存储器单元耦合到位线的第一和第二串联连接的虚拟晶体管。第一和第二存储单元串的第一虚拟存储单元具有共同连接到第一虚拟字线并具有不同阈值电压的栅极，并且第一和第二存储单元串的第二虚拟存储单元具有共同连接到第二虚位线并具有不同的阈值电压。在一些实施例中，第一存储单元串的第一虚拟存储单元和第二存储单元串的第二空存储单元可以具有大于预定电压的阈值电压，并且第一存储单元串的第二空存储单元和第二存储单元串的第一虚拟存储单元可以具有小于预定电压的阈值电压。

72. 发明授权

US09864682B2 Nonvolatile memory device and storage device having the same and operation method thereof 有权
公开(公告)号：US09864682B2
公开(公告)日：2018-01-09
申请号：US14664125
申请日：2015-03-20
申请人： Doohyun Kim , BoGeun Kim , Kitae Park , Jinman Han
发明人： Doohyun Kim , BoGeun Kim , Kitae Park , Jinman Han
IPC分类号： G06F12/02 , G11C11/56 , G11C16/04
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/0483
摘要： According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.

73. 发明申请

US20160322107A1 3D FLASH MEMORY DEVICE HAVING DIFFERENT DUMMY WORD LINES AND DATA STORAGE DEVICES INCLUDING SAME 审中-公开
标题翻译：具有不同密码字线的3D闪存存储器件和包括其中的数据存储器件
公开(公告)号：US20160322107A1
公开(公告)日：2016-11-03
申请号：US15210628
申请日：2016-07-14
申请人： SANG-WAN NAM , KITAE PARK
发明人： SANG-WAN NAM , KITAE PARK
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/08
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3427
摘要： A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.
摘要翻译：三维（3D）闪速存储器包括设置在接地选择线和最下面的主字线之间的第一虚拟字线和设置在弦选择线和最上主字线之间的不同字线配置的第二虚拟字线字线。

74. 发明授权

US09424947B2 Nonvolatile memory device and method of program verifying the same 有权
标题翻译：非易失性存储器件和程序验证方法
公开(公告)号：US09424947B2
公开(公告)日：2016-08-23
申请号：US14284031
申请日：2014-05-21
申请人： Donghun Kwak , Hyun-Wook Park , Kitae Park
发明人： Donghun Kwak , Hyun-Wook Park , Kitae Park
IPC分类号： G11C16/34 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： A program method of a three-dimensional nonvolatile memory device is provided which includes executing at least one program loop including an operation of programming selected memory cells of a selected string turned on by a selected string selection transistor and an operation of verifying whether programming of the memory cells is passed; and applying a negative counter voltage to a selected word line connected to the selected memory cells of the selected string at least once during an interval of the verify operation where there are turned on string selection transistors of unselected strings connected through the same bit line as that of the selected string.
摘要翻译：提供了一种三维非易失性存储器件的编程方法，包括执行至少一个程序循环，该程序循环包括对由所选择的字符串选择晶体管导通的所选字符串的选定存储单元进行编程的操作，以及验证是否记忆细胞通过; 以及在验证操作的间隔期间至少一次将连接到所选字符串的所选择的存储单元的选定字线施加负的反电压，其中通过与该相同的位线连接的未选择的串连接的串选择晶体管，的所选字符串。

75. 发明申请

US20150332777A1 STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF 审中-公开
标题翻译：包含非易失性存储器件的存储器件及其读取方法
公开(公告)号：US20150332777A1
公开(公告)日：2015-11-19
申请号：US14692494
申请日：2015-04-21
申请人： SANGYONG YOON , DONGHUN KWAK , KITAE PARK , MYUNG-HOON CHOI , SEUNG-CHEOL HAN
发明人： SANGYONG YOON , DONGHUN KWAK , KITAE PARK , MYUNG-HOON CHOI , SEUNG-CHEOL HAN
IPC分类号： G11C16/26 , G06F11/10 , G11C29/52 , G11C16/04
CPC分类号： G11C16/26 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/0466 , G11C16/0483 , G11C29/52 , G11C2013/0057
摘要： A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data.
摘要翻译：非易失性存储器件的读取方法包括根据第一读取电压从非易失性存储器件的选定存储区读取数据; 检测和校正读取数据的错误; 以及当读取的数据的错误是不可校正时，决定用于读取所选择的存储区域的第二读取电压。第二读取电压根据读取数据中包括的逻辑0或1的数量，或读取数据中的逻辑1与逻辑0的比率来决定。

76. 发明申请

US20150270008A1 NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE HAVING THE SAME AND OPERATION METHOD THEREOF 有权
标题翻译：非易失存储器件及其存储器件及其操作方法
公开(公告)号：US20150270008A1
公开(公告)日：2015-09-24
申请号：US14664125
申请日：2015-03-20
申请人： Doohyun KIM , BoGeun KIM , Kitae PARK , Jinman HAN
发明人： Doohyun KIM , BoGeun KIM , Kitae PARK , Jinman HAN
IPC分类号： G11C16/34 , G11C16/24 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/0483
摘要： According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.
摘要翻译：根据示例性实施例，一种操作存储设备的方法包括使用存储器控制器读取过程能力指数，基于过程能力指数来调整至少一个操作条件，以及根据at处理至少一个非易失性存储器设备调整至少一个操作条件。过程能力指数指示与要操作的存储器单元相关联的结构如何偏离目标形状。

77. 发明申请

US20150221351A1 NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING WORD LINE OF THE NONVOLATILE MEMORY 有权
标题翻译：非易失性存储器件的驱动和非易失性存储器的字线的方法
公开(公告)号：US20150221351A1
公开(公告)日：2015-08-06
申请号：US14567652
申请日：2014-12-11
申请人： SANG-WON PARK , KITAE PARK , SANG-WON SHIM
发明人： SANG-WON PARK , KITAE PARK , SANG-WON SHIM
IPC分类号： G11C7/12 , G11C7/04 , G11C7/10 , G11C5/02
CPC分类号： G11C8/08 , G11C5/02 , G11C7/04 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/30 , G11C16/32
摘要： A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.
摘要翻译：字线驱动方法是用于非易失性存储器件，其包括具有多个串的多个存储块，所述多个存储块形成在与衬底垂直的方向上并连接在位线和公共源极线之间。该方法包括将偏移脉冲施加到字线预定时间以缩短字线设置时间，并且在预定的时间之后将具有高于或低于偏移脉冲的电平的电平的目标脉冲施加到字线时间。

78. 发明授权

US09026749B2 Data storage system having multi-bit memory device and on-chip buffer program method thereof 有权
标题翻译：具有多位存储器件的数据存储系统及其片上缓冲器程序方法
公开(公告)号：US09026749B2
公开(公告)日：2015-05-05
申请号：US13484712
申请日：2012-05-31
申请人： Sangyong Yoon , Kitae Park
发明人： Sangyong Yoon , Kitae Park
IPC分类号： G06F12/00 , G11C11/56 , G06F12/02 , G11C16/34
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7203 , G11C16/3418 , G11C16/3454 , G11C2211/5641
摘要： Disclosed is an on-chip buffer program method for a data storage device which comprises a multi-bit memory device and a memory controller. The on-chip buffer program method includes measuring a performance of the data storage device, judging whether the measured performance satisfies a target performance of the data storage device, and selecting one of a plurality of scheduling manners as an on-chip buffer program scheduling manner of the data storage device according to the judgment result.
摘要翻译：公开了一种用于数据存储设备的片上缓冲器程序方法，其包括多位存储器件和存储器控制器。片上缓冲程序方法包括测量数据存储装置的性能，判断测量性能是否满足数据存储装置的目标性能，并选择多种调度方式之一作为片上缓冲程序调度方式的数据存储装置。

79. 发明授权

US09021338B2 Memory system and data storage method 有权
标题翻译：内存系统和数据存储方式
公开(公告)号：US09021338B2
公开(公告)日：2015-04-28
申请号：US13604772
申请日：2012-09-06
申请人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jaeyong Jeong
发明人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jaeyong Jeong
IPC分类号： G06F11/10 , G11C29/42 , G06F3/06 , H03M13/05 , H03M13/37 , G06F12/02 , G06F11/14
CPC分类号： G06F11/1048 , G06F3/0649 , G06F11/1068 , G06F11/14 , G06F11/1402 , G06F12/0246 , G06F2212/72 , G06F2212/7205 , G11C29/42 , G11C2211/5641 , H03M13/05 , H03M13/3715
摘要： A memory system comprises a nonvolatile memory device comprising a memory cell array comprising first and second memory blocks, and a memory controller configured to control the nonvolatile memory device to read data from the first memory block, selectively determine an error correction operation to be performed on the data after it is read from the first memory block based on a state of at least one of the first and second memory blocks, and then store the data in the second memory block.
摘要翻译：存储器系统包括非易失性存储器件，其包括包括第一和第二存储器块的存储器单元阵列，以及存储器控制器，其被配置为控制非易失性存储器件从第一存储器块读取数据，选择性地确定要执行的纠错操作基于第一和第二存储器块中的至少一个的状态从第一存储器块读取之后的数据，然后将数据存储在第二存储器块中。

80. 发明申请

US20150078098A1 NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF 审中-公开
标题翻译：非易失性存储器件及其程序方法
公开(公告)号：US20150078098A1
公开(公告)日：2015-03-19
申请号：US14302087
申请日：2014-06-11
申请人： DongHun KWAK , Kitae PARK
发明人： DongHun KWAK , Kitae PARK
IPC分类号： G11C16/10
CPC分类号： G11C16/24 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3418 , G11C16/3422 , G11C16/3427 , G11C16/3431
摘要： According to example embodiments of inventive concepts, a nonvolatile memory device includes at least two strings that are vertically stacked on a substrate and share one bit line. A program method of the nonvolatile memory device includes setting a pre-charge condition on the basis of a disturb environment between the at least two cell strings, pre-charging or not pre-charging an unselected cell string among the at least two cell strings in response to the pre-charge condition and programming memory cells in a selected cell string among the at least two cell strings.
摘要翻译：根据发明构思的示例性实施例，非易失性存储器件包括垂直堆叠在衬底上并且共享一个位线的至少两个串。非易失性存储装置的编程方法包括基于至少两个单元串之间的干扰环境来设置预充电状态，对至少两个单元串之间的未选择的单元串进行预充电或不预充电对所述预充电状态的响应以及在所述至少两个单元串中的所选单元串中编程存储器单元。

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