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71. 发明申请

US20110233789A1 ADHESIVE-BONDED SUBSTRATES IN A MULTI-CHIP MODULE 有权
标题翻译：多芯片模块中粘合的基板
公开(公告)号：US20110233789A1
公开(公告)日：2011-09-29
申请号：US12730823
申请日：2010-03-24
申请人： Robert J. Drost , Ashok V. Krishnamoorthy , John E. Cunningham
发明人： Robert J. Drost , Ashok V. Krishnamoorthy , John E. Cunningham
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L23/48 , H01L23/5389 , H01L2224/16145 , H01L2224/16225 , H01L2225/06531 , H01L2225/06555 , H01L2924/15153
摘要： A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces.
摘要翻译：描述了一种多芯片模块（MCM），其中至少两个基板通过粘合剂层机械耦合，所述粘合剂层在基板的表面上的接近连接器之间保持对准和零（或接近零）的间隔，从而有利于高信号质量基板之间的接近连接。为了提供足够的剪切强度，粘合剂层的厚度大于间隔。这可以使用衬底上的一个或多个正和/或负特征来实现。例如，粘合剂可以结合到：一个表面和在另一个表面下方凹进的通道的内表面; 在两个表面下凹陷的通道的内表面; 或两个表面。在最后一种情况下，零（或接近零）的间距可以通过将接近连接器设置在突出在至少一个衬底表面上的台面上来实现。

72. 发明申请

US20110111559A1 INTEGRATED-CIRCUIT PACKAGE FOR PROXIMITY COMMUNICATION 有权
标题翻译：用于接近通信的集成电路封装
公开(公告)号：US20110111559A1
公开(公告)日：2011-05-12
申请号：US13006227
申请日：2011-01-13
申请人： James G. Mitchell , John E. Cunningham , Ashok V. Krishnamoorthy
发明人： James G. Mitchell , John E. Cunningham , Ashok V. Krishnamoorthy
IPC分类号： H01L21/50
CPC分类号： H01L25/0652 , H01L23/10 , H01L23/48 , H01L24/02 , H01L24/16 , H01L24/72 , H01L24/81 , H01L24/95 , H01L25/50 , H01L2224/0401 , H01L2224/13099 , H01L2224/73251 , H01L2224/81136 , H01L2224/81801 , H01L2224/95136 , H01L2225/06513 , H01L2225/06531 , H01L2225/06534 , H01L2225/06593 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01067 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10157 , H01L2924/10158 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/351 , H01L2924/00 , H01L2224/16 , H01L2224/72
摘要： Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.
摘要翻译：描述了多芯片模块（MCM）的实施例。该MCM包括第一半导体管芯和第二半导体管芯，其中可以是第一半导体管芯或第二半导体管芯的给定半导体管芯包括靠近给定半导体管芯的表面的接近连接器。此外，给定的半导体管芯被配置为通过一个或多个接近连接器的接近通信与另一个半导体管芯通信信号。此外，MCM包括对准板和联接到对准板的顶板。该对准板包括被配置为容纳第一半导体管芯的第一负特征构件和被配置为容纳第二半导体管芯的第二负特征，并且顶板包括正特征。注意，正特征耦合到第一半导体管芯，并且正特征有利于第一半导体管芯的机械定位。

73. 发明授权

US07893531B2 Integrated-circuit package for proximity communication 有权
公开(公告)号：US07893531B2
公开(公告)日：2011-02-22
申请号：US11864408
申请日：2007-09-28
申请人： James G. Mitchell , John E. Cunningham , Ashok V. Krishnamoorthy
发明人： James G. Mitchell , John E. Cunningham , Ashok V. Krishnamoorthy
IPC分类号： H01L23/34
CPC分类号： H01L25/0652 , H01L23/10 , H01L23/48 , H01L24/02 , H01L24/16 , H01L24/72 , H01L24/81 , H01L24/95 , H01L25/50 , H01L2224/0401 , H01L2224/13099 , H01L2224/73251 , H01L2224/81136 , H01L2224/81801 , H01L2224/95136 , H01L2225/06513 , H01L2225/06531 , H01L2225/06534 , H01L2225/06593 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01058 , H01L2924/01067 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10157 , H01L2924/10158 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/351 , H01L2924/00 , H01L2224/16 , H01L2224/72
摘要： Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.

74. 发明授权

US07888175B2 Method and apparatus for facilitating proximity communication and power delivery 有权
标题翻译：用于促进邻近通信和电力传递的方法和装置
公开(公告)号：US07888175B2
公开(公告)日：2011-02-15
申请号：US12502156
申请日：2009-07-13
申请人： Ashok V. Krishnamoorthy , John E. Cunningham
发明人： Ashok V. Krishnamoorthy , John E. Cunningham
IPC分类号： H01L21/60 , H01L29/40
CPC分类号： H01L23/48 , G02B6/12007 , G02B6/29341 , G02B6/43 , H01L24/10 , H01L24/13 , H01L24/72 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L2224/05556 , H01L2224/05572 , H01L2224/05573 , H01L2224/056 , H01L2224/10135 , H01L2224/10165 , H01L2224/13 , H01L2224/13099 , H01L2224/1319 , H01L2224/2919 , H01L2224/81138 , H01L2224/81141 , H01L2224/81801 , H01L2224/83141 , H01L2224/83194 , H01L2224/838 , H01L2224/83851 , H01L2225/06527 , H01L2924/01006 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/10157 , H01L2924/14 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： The described embodiments provide a system that facilitates inter-chip alignment for proximity communication and power delivery. The system includes a first integrated circuit chip and a second integrated circuit chip, both of which whose surfaces have corresponding etch pit wells configured to align with each other. A shaped structure is placed in an etch pit well of the first integrated circuit chip such that when the corresponding etch pit well of the second integrated circuit chip is substantially aligned with the etch pit well of the first integrated circuit chip, the shaped structure mates with both the etch pit well of the first integrated circuit chip and with the corresponding etch pit well of the second integrated circuit chip, thereby aligning the first integrated circuit chip with the second integrated circuit chip. In some embodiments the etch pit wells include conductive structures for routing power through a conductive shaped structure.
摘要翻译：所描述的实施例提供了一种促进接近通信和功率传递的芯片间对准的系统。该系统包括第一集成电路芯片和第二集成电路芯片，它们的两个表面具有被配置为彼此对准的相应蚀刻凹坑。成形结构放置在第一集成电路芯片的蚀刻凹坑中，使得当第二集成电路芯片的相应蚀刻凹坑与第一集成电路芯片的蚀刻凹坑基本对准时，成形结构与第一集成电路芯片的蚀刻凹坑以及第二集成电路芯片的相应蚀刻凹坑两者，从而使第一集成电路芯片与第二集成电路芯片对准。在一些实施例中，蚀刻坑井包括用于通过导电成形结构路由功率的导电结构。

75. 发明申请

US20100247029A1 THERMAL TUNING OF AN OPTICAL DEVICE 有权
标题翻译：光学装置的热调谐
公开(公告)号：US20100247029A1
公开(公告)日：2010-09-30
申请号：US12415882
申请日：2009-03-31
申请人： Guoliang Li , Ashok V. Krishnamoorthy , John E. Cunningham , Ivan Shubin , Xuezhe Zheng
发明人： Guoliang Li , Ashok V. Krishnamoorthy , John E. Cunningham , Ivan Shubin , Xuezhe Zheng
IPC分类号： G02B6/12
CPC分类号： G02B6/12007 , G02B2006/12061 , G02F1/011 , G02F1/0147 , G02F2202/10
摘要： Embodiments of an optical device, an array of optical devices, and a technique for fabricating the optical device or the array are described. This optical device is implemented on a substrate (such as silicon), and includes a thermally tunable optical waveguide with a high thermal resistance to the surrounding external environment and a low thermal resistance to a localized heater. In particular, the thermal resistances associated with thermal dissipation paths from a heater in the optical device to an external environment via electrodes and via the substrate are increased, while the thermal resistance between the optical waveguide and the heater is decreased.
摘要翻译：描述了光学器件，光学器件阵列以及用于制造光学器件或阵列的技术的实施例。该光学器件实现在基板（例如硅）上，并且包括具有对周围外部环境的高耐热性和对局部加热器的低热阻的热可调谐光波导。特别地，与通过电极和经由基板的从光学装置中的加热器到外部环境的热耗散路径相关联的热阻增加，同时光波导和加热器之间的热阻降低。

76. 发明授权

US07646984B1 Clocking of integrated circuits using photonics 有权
标题翻译：使用光子学的集成电路的时钟
公开(公告)号：US07646984B1
公开(公告)日：2010-01-12
申请号：US11728915
申请日：2007-03-26
申请人： Ronald Ho , John E. Cunningham , Ashok V. Krishnamoorthy , Robert J. Drost
发明人： Ronald Ho , John E. Cunningham , Ashok V. Krishnamoorthy , Robert J. Drost
IPC分类号： H04B10/12
CPC分类号： G06F1/105
摘要： Embodiments of an integrated circuit are described. This integrated circuit includes: a clock-generator circuit configured to provide a clock signal; an optical clock path coupled to the clock-generator circuit; and a latch coupled to the optical clock path. This optical clock path is configured to distribute an optical signal corresponding to the clock signal. Furthermore, the optical clock path is configured to optically set a skew value for the optical signal, and is configured to selectively gate distribution of the optical signal to the latch based on activity of the latch. Note that the selective gating is performed optically.
摘要翻译：描述集成电路的实施例。该集成电路包括：时钟发生器电路，被配置为提供时钟信号; 耦合到时钟发生器电路的光时钟通路; 以及耦合到光时钟路径的锁存器。该光时钟路径被配置为分配对应于时钟信号的光信号。此外，光时钟路径被配置为光学地设置光信号的偏斜值，并且被配置为基于锁存器的活动来选择性地将光信号分配到锁存器。注意，选择性门控是光学执行的。

77. 发明申请

US20090280601A1 METHOD AND APPARATUS FOR FACILITATING PROXIMITY COMMUNICATION AND POWER DELIVERY 有权
标题翻译：促进接近通信和电力交付的方法和装置
公开(公告)号：US20090280601A1
公开(公告)日：2009-11-12
申请号：US12502156
申请日：2009-07-13
申请人： Ashok V. Krishnamoorthy , John E. Cunningham
发明人： Ashok V. Krishnamoorthy , John E. Cunningham
IPC分类号： H01L21/50
CPC分类号： H01L23/48 , G02B6/12007 , G02B6/29341 , G02B6/43 , H01L24/10 , H01L24/13 , H01L24/72 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L2224/05556 , H01L2224/05572 , H01L2224/05573 , H01L2224/056 , H01L2224/10135 , H01L2224/10165 , H01L2224/13 , H01L2224/13099 , H01L2224/1319 , H01L2224/2919 , H01L2224/81138 , H01L2224/81141 , H01L2224/81801 , H01L2224/83141 , H01L2224/83194 , H01L2224/838 , H01L2224/83851 , H01L2225/06527 , H01L2924/01006 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/0665 , H01L2924/10157 , H01L2924/14 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： The described embodiments provide a system that facilitates inter-chip alignment for proximity communication and power delivery. The system includes a first integrated circuit chip and a second integrated circuit chip, both of which whose surfaces have corresponding etch pit wells configured to align with each other. A shaped structure is placed in an etch pit well of the first integrated circuit chip such that when the corresponding etch pit well of the second integrated circuit chip is substantially aligned with the etch pit well of the first integrated circuit chip, the shaped structure mates with both the etch pit well of the first integrated circuit chip and with the corresponding etch pit well of the second integrated circuit chip, thereby aligning the first integrated circuit chip with the second integrated circuit chip. In some embodiments the etch pit wells include conductive structures for routing power through a conductive shaped structure.
摘要翻译：所描述的实施例提供了一种促进接近通信和功率传递的芯片间对准的系统。该系统包括第一集成电路芯片和第二集成电路芯片，它们的两个表面具有被配置为彼此对准的相应蚀刻凹坑。成形结构放置在第一集成电路芯片的蚀刻凹坑中，使得当第二集成电路芯片的相应蚀刻凹坑与第一集成电路芯片的蚀刻凹坑基本对准时，成形结构与第一集成电路芯片的蚀刻凹坑以及第二集成电路芯片的相应蚀刻凹坑两者，从而使第一集成电路芯片与第二集成电路芯片对准。在一些实施例中，蚀刻坑井包括用于通过导电成形结构路由功率的导电结构。

78. 发明申请

US20090179334A1 APPARATUS FOR FACILITATING PROXIMITY COMMUNICATION BETWEEN CHIPS 有权
标题翻译：用于促进CHIPS之间的接近通信的装置
公开(公告)号：US20090179334A1
公开(公告)日：2009-07-16
申请号：US12391137
申请日：2009-02-23
申请人： Ashok V. Krishnamoorthy , John E. Cunningham
发明人： Ashok V. Krishnamoorthy , John E. Cunningham
IPC分类号： H01L23/482
CPC分类号： H01L23/48 , H01L25/0652 , H01L25/50 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip.
摘要翻译：本发明的一个实施例提供一种用于促进半导体芯片之间的邻近通信的系统。该系统包括一个基片和一个桥芯片，每个芯片包括有源电路和信号焊盘所在的有源面以及与有源面相对的背面。桥芯片的主动面接合到基片的有源面。然后，通过蚀刻使桥接芯片的有源面的识别部分变薄，并且通过平坦化桥芯片的背面去除，从而在桥芯片中形成露出基片的有源面的一部分的开口。

79. 发明授权

US07356213B1 Transparent switch using optical and electrical proximity communication 有权
标题翻译：透明开关采用光电接近通讯
公开(公告)号：US07356213B1
公开(公告)日：2008-04-08
申请号：US11728843
申请日：2007-03-26
申请人： John E. Cunningham , Ashok V. Krishnamoorthy , Ronald Ho , Robert J. Drost
发明人： John E. Cunningham , Ashok V. Krishnamoorthy , Ronald Ho , Robert J. Drost
IPC分类号： G02B6/12
CPC分类号： H01L23/48 , H01L25/0652 , H01L25/0657 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of a switch are described. This switch includes input ports configured to receive signals (which include data) and output ports configured to output the signals. In addition, the switch includes switching elements and a flow-control mechanism, which is configured to provide flow-control information associated with the data to the switching elements via an optical control path. These switching elements are configured to selectively couple the input ports to the output ports based on the flow-control information. Furthermore, a given switching element in the switching elements is coupled to a given input port and a given output port via electrical signal paths that are configured to use proximity communication to communicate the data.
摘要翻译：描述开关的实施例。该开关包括被配置为接收被配置为输出信号的信号（其包括数据）和输出端口的输入端口。此外，开关包括开关元件和流量控制机构，其被配置为经由光学控制路径向开关元件提供与数据相关联的流量控制信息。这些开关元件被配置为基于流量控制信息选择性地将输入端口耦合到输出端口。此外，开关元件中的给定开关元件通过经配置以使用接近通信来传送数据的电信号路径耦合到给定输入端口和给定输出端口。

80. 发明授权

US5468689A Method for preparation of silicon nitride gallium diffusion barrier for use in molecular beam epitaxial growth of gallium arsenide 失效
标题翻译：制备用于砷化镓分子束外延生长的氮化硅镓扩散阻挡层的方法
公开(公告)号：US5468689A
公开(公告)日：1995-11-21
申请号：US153719
申请日：1993-11-16
申请人： John E. Cunningham , Keith W. Goossen , William Y. Jan , James A. Walker
发明人： John E. Cunningham , Keith W. Goossen , William Y. Jan , James A. Walker
IPC分类号： C23C16/50 , H01L21/203 , H01L21/205 , H01L21/318 , H01L21/02 , H01L21/20
CPC分类号： H01L21/3185 , Y10S438/933
摘要： A technique is described for the preparation of a thin film of a silicon nitride diffusion barrier to gallium on a silicon integrated circuit chip. The technique involves reacting nitrogen and silane in a ratio of 53:1 to 300:1 in a plasma enhanced chemical vapor deposition apparatus. The described technique is of interest for use in the monolithic integration of interconnected GaAs/AlGaAs double heterostructures, modulators and silicon MOSFET structures.
摘要翻译：描述了一种用于在硅集成电路芯片上制备氮化硅扩散阻挡层至镓的薄膜的技术。该技术涉及在等离子体增强化学气相沉积装置中使氮和硅烷以53:1至300:1的比例反应。所描述的技术对于用于互连的GaAs / AlGaAs双异质结构，调制器和硅MOSFET结构的单片集成是有意义的。

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