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71. 发明授权

US06766381B1 VLSI network processor and methods 失效
标题翻译： VLSI网络处理器和方法
公开(公告)号：US06766381B1
公开(公告)日：2004-07-20
申请号：US09384689
申请日：1999-08-27
申请人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Kenneth James Barker , Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1516
CPC分类号： H04L29/06 , H04L49/1507 , H04L49/45 , H04L69/12
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成在半导体衬底上的指令存储器中的指令的控制下操作。

72. 发明授权

US06675163B1 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US06675163B1
公开(公告)日：2004-01-06
申请号：US09543531
申请日：2000-04-06
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1730
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n→n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。用于存储散列键和树中相关信息的数据结构称为叶。每个叶对应于与输入键完全匹配的单个键。叶包含关键以及其他信息。叶片的长度是可编程的，密钥的长度也是可编程的。叶存储在随机存取存储器中，并被实现为单个存储器条目。如果键位于直接表中，则称为直接叶。

73. 发明授权

US06657962B1 Method and system for managing congestion in a network 失效
标题翻译：管理网络拥塞的方法和系统
公开(公告)号：US06657962B1
公开(公告)日：2003-12-02
申请号：US09546651
申请日：2000-04-10
申请人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
发明人： Peter Irma August Barri , Brian Mitchell Bass , Jean Louis Calvignac , Ivan Oscar Clemminck , Marco C. Heddes , Clark Debs Jeffries , Michael Steven Siegel , Fabrice Jean Verplanken , Miroslav Vrana
IPC分类号： H04L1256
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/12 , H04L47/30 , H04L47/32 , H04L49/103 , H04L49/3018 , H04L49/50 , H04L49/90
摘要： A system for minimizing congestion in a communication system is disclosed. The system comprises at least one ingress system for providing data. The ingress system includes a first free queue and a first flow queue. The system also includes a first congestion adjustment module for receiving congestion indications from the free queue and the flow queue. The first congestion adjustment module generates end stores transmit probabilities and performs per packet flow control actions. The system further includes a switch fabric for receiving data from the ingress system and for providing a congestion indication to the ingress system. The system further includes at least one egress system for receiving the data from the switch fabric. The egress system includes a second free queue and a second flow queue. The system also includes a second congestion adjustment module for receiving congestion indications from the second free queue and the second flow queue. The second congestion adjustment module generates and stores transmit probabilities and performs per packet flow control actions. Finally, the system includes a scheduler for determining the order and timing of transmission of packets out the egress system and to another node or destination. A method and system in accordance with the present invention provides for a unified method and system for logical connection of congestion with the appropriate flow control responses. The method and system utilizes congestion indicators within the ingress system, egress system, and the switch fabric in conjunction with a coarse adjustment system and fine adjustment system within the ingress device and the egress device to intelligently manage the system.
摘要翻译：公开了一种用于最小化通信系统中的拥塞的系统。该系统包括用于提供数据的至少一个入口系统。入口系统包括第一空闲队列和第一流队列。该系统还包括用于从空闲队列和流队列接收拥塞指示的第一拥塞调整模块。第一拥塞调整模块生成终端存储发送概率并执行每个分组流控制动作。该系统还包括用于从入口系统接收数据并向入口系统提供拥塞指示的交换结构。该系统还包括用于从交换结构接收数据的至少一个出口系统。出口系统包括第二空闲队列和第二流队列。该系统还包括第二拥塞调整模块，用于从第二空闲队列和第二流队列接收拥塞指示。第二拥塞调整模块生成并存储发送概率，并执行每个分组流控制动作。最后，该系统包括一个调度器，用于确定出口系统和另一个节点或目的地的分组传输的顺序和定时。根据本发明的方法和系统提供了用于将拥塞与适当流控制响应逻辑连接的统一方法和系统。该方法和系统利用入口系统，出口系统和交换结构中的拥塞指示符与入口设备和出口设备内的粗调系统和精细调整系统结合，智能地管理系统。

74. 发明授权

US06522271B2 Method and apparatus for transmission on a 2-bit channel using 3b/4b code 失效
公开(公告)号：US06522271B2
公开(公告)日：2003-02-18
申请号：US10096161
申请日：2002-03-12
申请人： Jean Louis Calvignac , Jeffrey James Lynch , Daniel James Sucher , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Jeffrey James Lynch , Daniel James Sucher , Fabrice Jean Verplanken
IPC分类号： H03M700
CPC分类号： H03M7/20
摘要： A 2-bit communication channel is made to transmit complex data patterns by partitioning a digital string into 3-bit binary patterns which are encoded into 4 bits binary pattern and transmitted over the 2-bit communication channel in pairs using adjacent clock cycles on the 2-bit channel. Pre-defined ones of the 4-bit encoded data structures are used for framing on the channel and cannot be used to transmit data.

75. 发明申请

US20160085722A1 DATA PACKET PROCESSING 有权
标题翻译：数据包处理
公开(公告)号：US20160085722A1
公开(公告)日：2016-03-24
申请号：US14862599
申请日：2015-09-23
申请人： Fabrice Jean VERPLANKEN , Francois ABEL , Claude BASSO , Damon PHILIPPE
发明人： Fabrice Jean VERPLANKEN , Francois ABEL , Claude BASSO , Damon PHILIPPE
IPC分类号： G06F15/80 , G06F13/42 , G06F13/40
CPC分类号： G06F13/4282 , G06F13/4022
摘要： Proposed is an action machine for processing packet data in a network processor. The action machine comprises: first and second data storage units adapted to store data for processing; and a processing unit adapted to process data from the first and second data storage units. The first storage unit is adapted to be accessed by the processing unit and a unit external to the action machine, and the second storage unit is adapted to only be accessed by the processing unit.
摘要翻译：提出了一种在网络处理器中处理分组数据的动作机器。动作机器包括：适于存储用于处理的数据的第一和第二数据存储单元; 以及适于处理来自第一和第二数据存储单元的数据的处理单元。第一存储单元适于由处理单元访问和操作机外部的单元，并且第二存储单元仅适于由处理单元访问。

76. 发明授权

US08942095B2 Identification of QoS classification based on packet attributes 有权
标题翻译：基于分组属性的QoS分类识别
公开(公告)号：US08942095B2
公开(公告)日：2015-01-27
申请号：US13302489
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/54 , H04L12/851 , H04L29/06
CPC分类号： H04L47/2441 , H04L69/22
摘要： A method, a system, and a computer program product is disclosed for identifying a quality of service (QoS) classification of a packet in a network by a network processor. The method comprising: providing a table wherein a priority value with a maximum of N values is used as an index into the table to retrieve a QoS classification having a maximum of M values with M less than N; receiving a data packet in a stream of data packets; extracting at least two priority indicator values from the packet; converting the at least two priority indicator values into a priority value; utilizing the priority value as an index into the table; extracting the entry in the table corresponding to the priority value as the QoS classification of the packet; and utilizing the QoS classification for subsequent processing of the data packet.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于通过网络处理器来识别网络中的分组的服务质量（QoS）分类。该方法包括：提供一个表，其中将具有最大N个值的优先级值用作表中的索引以检索具有M小于N的最大M个值的QoS分类; 在数据包流中接收数据包; 从分组中提取至少两个优先级指示符值; 将所述至少两个优先级指示符值转换为优先级值; 利用优先级值作为表中的索引; 提取对应于优先级值的表中的条目作为分组的QoS分类; 并利用QoS分类来对数据分组进行后续处理。

77. 发明申请

US20120221928A1 CHECKSUM VERIFICATION ACCELERATOR 有权
标题翻译：检查验证加速器
公开(公告)号：US20120221928A1
公开(公告)日：2012-08-30
申请号：US13466940
申请日：2012-05-08
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H04L1/0079 , H04L1/0061 , H04L1/0072
摘要： Disclosed a method for validating a data packet by a network processor supporting a first, network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet: identities a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The method produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The method validates the data packet by comparing the data packet checksum to the second checksum.
摘要翻译：公开了一种通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法。网络处理器接收数据包：识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理，包括：以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。该方法利用组合来自第一寄存器，第二寄存器和第三寄存器的值的函数产生第二校验和。该方法通过将数据包校验和与第二校验和进行比较来验证数据包。

78. 发明授权

US08225188B2 Apparatus for blind checksum and correction for network transmissions 有权
标题翻译：用于网络传输的盲校验和校正装置
公开(公告)号：US08225188B2
公开(公告)日：2012-07-17
申请号：US12200985
申请日：2008-08-29
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H03M13/00
CPC分类号： H04L69/16 , H04L1/0041 , H04L1/0061 , H04L1/0072 , H04L69/161
摘要： Apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.
摘要翻译：用于在网络传输中提供校验和的装置。在本发明的一个方面，通过从存储设备检索分组信息来确定要在网络上发送的分组的校验和，所述分组信息将包括在要发送的分组中。基于检索的分组信息确定盲校验和值，并且基于描述分组的结构的描述符信息将盲校验和值调整为协议校验和。在分组发送之前，协议校验和被插入到分组中。

79. 发明授权

US08195705B2 Hybrid search memory for network processor and computer systems 有权
标题翻译：用于网络处理器和计算机系统的混合搜索存储器
公开(公告)号：US08195705B2
公开(公告)日：2012-06-05
申请号：US10015165
申请日：2001-12-11
申请人： Jean Louis Calvignac , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Fabrice Jean Verplanken
IPC分类号： G06F17/30
CPC分类号： G06F17/30327
摘要： A system includes a data structure having a Direct Table (DT), Patricia-Trees, Pointers and high speed storage systems such as Contents Address Memory (CAM). The DT has a plurality of entries with each one coupled to a Patricia Tree having multiple nodes coupled to leaves. The number of Nodes, termed a threshold, that can be traversed to obtain information in the leaves is limited to a predetermined value. Once the threshold is reached a pointer indicates the address of the CAM and the address of the leaves is stored in the CAM. By using the structure and method the latency associated with tree search is significantly reduced.
摘要翻译：系统包括具有直接表（DT），帕特里夏树，指针和诸如内容地址存储器（CAM）的高速存储系统的数据结构。 DT具有多个条目，其中每个条目耦合到具有耦合到叶子的多个节点的Patricia Tree。被称为阈值的节点数量，可以被遍历以获得叶子中的信息被限制到预定值。一旦达到阈值，指针指示CAM的地址，并且叶子的地址被存储在CAM中。通过使用结构和方法，与树搜索相关联的延迟显着降低。

80. 发明授权

US08037439B2 Data aligner in reconfigurable computing environment 失效
标题翻译：可重构计算环境中的数据对齐器
公开(公告)号：US08037439B2
公开(公告)日：2011-10-11
申请号：US12126953
申请日：2008-05-26
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

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