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71. 发明授权

US06780731B1 HDP gap-filling process for structures with extra step at side-wall 失效
标题翻译： HDP间隙填充过程，用于侧壁额外加工的结构
公开(公告)号：US06780731B1
公开(公告)日：2004-08-24
申请号：US10225803
申请日：2002-08-22
申请人： Yeur-Luen Tu , Tsung-Hsun Huang , Chung-Yi Yu , Yuan-Hung Liu
发明人： Yeur-Luen Tu , Tsung-Hsun Huang , Chung-Yi Yu , Yuan-Hung Liu
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang. This approach is found to prevent the formation of an overhang at the position of the step, whereat it would cause progressive restriction of the trench throat and void formation.
摘要翻译：一种多步骤HDP沉积和溅射方法，用于无缝填充具有阶梯形横截面轮廓的高纵横比沟槽。该方法特别适用于填充形成在包括硅第一层，氧化物第二层和氮化物第三层的三层分层衬底中的沟槽，其中氮化物层从沟槽开口的边缘被拉回并形成一个台阶。该方法允许这种沟槽的无空隙填充，而不会使该过程中的氮化物层老化。简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比沉积，并且具有低偏压能力以在上表面形成具有突出端的层沟。该沉积如果随后是溅射工艺以在该突出端形成扩大的开口。发现这种方法可以防止在台阶位置形成突出端，从而导致沟槽喉部和空隙形成的逐渐限制。

72. 发明授权

US08884268B2 Diffusion barrier layer for group III nitride on silicon substrate 有权
标题翻译：硅衬底上III族氮化物的扩散阻挡层
公开(公告)号：US08884268B2
公开(公告)日：2014-11-11
申请号：US13549610
申请日：2012-07-16
申请人： Chi-Ming Chen , Han-Chin Chiu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chi-Ming Chen , Han-Chin Chiu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L21/44
CPC分类号： H01L21/02381 , H01L21/02458 , H01L21/02488 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and O2 from a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise Al2O3. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer.
摘要翻译：本公开涉及集成电路及其形成。在一些实施例中，集成电路包括扩散阻挡层。扩散阻挡层可以被布置成防止Si和O 2从Si衬底扩散到III族氮化物层中。扩散阻挡层可以包括Al 2 O 3。在一些实施例中，集成电路还包括设置在硅衬底和III族氮化物层之间的晶格匹配结构。

73. 发明授权

US08851133B2 Method and apparatus of holding a device 有权
标题翻译：握持装置的方法和装置
公开(公告)号：US08851133B2
公开(公告)日：2014-10-07
申请号：US12414861
申请日：2009-03-31
申请人： Martin Liu , Chung-Yi Yu , Che Ying Hsu , Yeur-Luen Tu , Da-Hsiang Chou , Chia-Shiung Tsai
发明人： Martin Liu , Chung-Yi Yu , Che Ying Hsu , Yeur-Luen Tu , Da-Hsiang Chou , Chia-Shiung Tsai
IPC分类号： C23C16/50 , C23C16/00 , C23F1/00 , H01L21/306 , H01L21/683
CPC分类号： H01L21/6838 , H01L21/304
摘要： Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.
摘要翻译：提供了一种保持装置的装置和方法。该装置包括具有穿过其延伸的第一和第二孔的晶片卡盘，以及压力控制结构，其能够在高于和低于环境压力的压力之间独立地和选择性地改变在第一和第二孔中的每一个中的流体压力。该方法包括提供具有延伸穿过其中的第一和第二孔的晶片卡盘，并且在高于和低于环境压力的压力之间独立地和选择性地改变在每个第一和第二孔中的流体压力。

74. 发明授权

US08809976B2 Method and structure for a MRAM device with a bilayer passivation 有权
标题翻译：具有双层钝化的MRAM器件的方法与结构
公开(公告)号：US08809976B2
公开(公告)日：2014-08-19
申请号：US13244346
申请日：2011-09-24
申请人： Chih-Ming Chen , Chung-Yi Yu , Cheng-Yuan Tsai , Kai-Wen Cheng
发明人： Chih-Ming Chen , Chung-Yi Yu , Cheng-Yuan Tsai , Kai-Wen Cheng
IPC分类号： H01L29/82 , H01L43/08 , H01L27/22 , G11C11/16 , B82Y25/00 , B82Y10/00
CPC分类号： H01L43/08 , B82Y10/00 , B82Y25/00 , G11C11/16 , H01L27/228 , H01L43/12
摘要： The present disclosure provides a magnetoresistive random access memory (MRAM) device. The MRAM device includes a magnetic tunnel junction (MTJ) stack on a substrate; and a dual-layer passivation layer disposed around the MTJ stack. The dual-layer passivation layer includes an oxygen-free film formed adjacent sidewalls of the MTJ stack; and a moisture-blocking film formed around the oxygen-free film.
摘要翻译：本公开提供了一种磁阻随机存取存储器（MRAM）装置。 MRAM器件包括在衬底上的磁隧道结（MTJ）堆叠; 以及设置在MTJ堆叠周围的双层钝化层。双层钝化层包括与MTJ叠层的侧壁相邻形成的无氧膜; 以及形成在无氧膜周围的防潮膜。

75. 发明授权

US08791504B2 Substrate breakdown voltage improvement for group III-nitride on a silicon substrate 有权
标题翻译：硅衬底上III族氮化物的衬底击穿电压提高
公开(公告)号：US08791504B2
公开(公告)日：2014-07-29
申请号：US13277692
申请日：2011-10-20
申请人： Chi-Ming Chen , Po-Chun Liu , Hung-Ta Lin , Chin-Cheng Chang , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
发明人： Chi-Ming Chen , Po-Chun Liu , Hung-Ta Lin , Chin-Cheng Chang , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
IPC分类号： H01L29/66
CPC分类号： H01L21/02381 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/517 , H01L29/66462 , H01L29/7787
摘要： A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.
摘要翻译：电路结构包括衬底，未掺杂的氮化铝的成核层，包含铝，镓，氮，硅和氧中的一种的梯度缓冲层和p型导电掺杂剂，包含镓，氮，一个的硅和氧，以及没有铝的p型导电掺杂物，以及未分级缓冲层上的未掺杂氮化镓的体层。分级缓冲层和未分级缓冲层中的各种掺杂剂增加了电阻率并导致具有本质上平衡的导电性的层。

76. 发明授权

US08772831B2 III-nitride growth method on silicon substrate 有权
标题翻译：硅衬底上的III族氮化物生长方法
公开(公告)号：US08772831B2
公开(公告)日：2014-07-08
申请号：US13290534
申请日：2011-11-07
申请人： Chi-Ming Chen , Po-Chun Liu , Hung-Ta Lin , Chin-Cheng Chang , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
发明人： Chi-Ming Chen , Po-Chun Liu , Hung-Ta Lin , Chin-Cheng Chang , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
IPC分类号： H01L29/267 , H01L29/778
CPC分类号： H01L33/007 , C30B25/183 , C30B29/403 , H01L21/02381 , H01L21/02458 , H01L21/0251 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L29/2003 , H01L29/66462
摘要： A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer.
摘要翻译：电路结构包括衬底和衬底上的图案化电介质层。图案化电介质层包括多个通孔; 和III族V族（III-V）族化合物半导体层。 III-V族化合物半导体层包括通孔中的第一层，第一层上的第二层和电介质层，以及在第二层上的体层。

77. 发明授权

US08629013B2 Junction leakage reduction through implantation 有权
标题翻译：通过植入减少结漏电
公开(公告)号：US08629013B2
公开(公告)日：2014-01-14
申请号：US13273463
申请日：2011-10-14
申请人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
发明人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
IPC分类号： H01L21/338
CPC分类号： H01L29/66522 , H01L21/2654 , H01L29/267
摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底上形成第一III-V族层。第一III-V族层包括具有第一表面形态的表面。该方法包括通过表面对第一III-V族层执行离子注入工艺。离子注入工艺将第一表面形态变为第二表面形态。在执行离子注入工艺之后，该方法包括在第一III-V族层上形成第二III-V族层。第二III-V族层具有不同于第一III-V族层的材料组成。

78. 发明申请

US20130075837A1 TECHNIQUE FOR SMOOTHING AN INTERFACE BETWEEN LAYERS OF A SEMICONDUCTOR DEVICE 有权
标题翻译：用于平滑半导体器件层之间的界面的技术
公开(公告)号：US20130075837A1
公开(公告)日：2013-03-28
申请号：US13240714
申请日：2011-09-22
申请人： Chih-Ming Chen , Cheng-Yuan Tsai , Chung-Yi Yu , Kai-Wen Cheng , Kuo-Ming Wu
发明人： Chih-Ming Chen , Cheng-Yuan Tsai , Chung-Yi Yu , Kai-Wen Cheng , Kuo-Ming Wu
IPC分类号： H01L29/82 , H01L21/8246
CPC分类号： H01L27/228 , H01L43/08 , H01L43/12
摘要： The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a composite layer disposed over the pinned layer, the composite layer having a magnetic material randomly distributed in a non-magnetic material; a barrier layer disposed on the composite layer; a free layer disposed over the barrier layer; and a second electrode disposed over the free layer.
摘要翻译：本公开提供一种半导体存储器件。该装置包括具有反铁磁材料并设置在第一电极上的钉扎层; 设置在钉扎层上方的钉扎层; 复合层，其设置在所述被钉扎层上方，所述复合层具有随机分布在非磁性材料中的磁性材料; 设置在所述复合层上的阻挡层; 设置在阻挡层上的自由层; 以及设置在所述自由层上方的第二电极。

79. 发明申请

US20120149176A1 METHOD AND APPARATUS FOR FORMING A III-V FAMILY LAYER 审中-公开
标题翻译：用于形成III-V族层的方法和装置
公开(公告)号：US20120149176A1
公开(公告)日：2012-06-14
申请号：US12964994
申请日：2010-12-10
申请人： Chi-Ming Chen , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
发明人： Chi-Ming Chen , Chung-Yi Yu , Chia-Shiung Tsai , Ho-Yung David Hwang
IPC分类号： H01L21/20 , C23C16/34
CPC分类号： C23C16/303 , C23C16/4401 , C23C16/54 , C23C16/56
摘要： Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool.
摘要翻译：提供了一种装置。该装置包括：第一沉积部件，其可操作以在半导体晶片上形成化合物，所述化合物包括III族元素和V族元素中的至少一种; 第二沉积组分，其可操作以在所述化合物上形成钝化层; 以及可操作以在所述第一和第二沉积部件之间移动所述半导体晶片的转移部件，所述转移部件包围基本上不含氧且基本上不含硅的空间; 其中装载部件，第一和第二沉积部件以及传送部件都被集成到单个制造工具中。

80. 发明申请

US20110177668A1 METHOD OF MAKING A THIN FILM RESISTOR 有权
标题翻译：制造薄膜电阻的方法
公开(公告)号：US20110177668A1
公开(公告)日：2011-07-21
申请号：US12688083
申请日：2010-01-15
申请人： Der-Chyang YEH , Hsun-Chung KUANG , Ming Chyi LIU , Chung-Yi YU , Chih-Ping CHAO , Alexander KALNITSKY
发明人： Der-Chyang YEH , Hsun-Chung KUANG , Ming Chyi LIU , Chung-Yi YU , Chih-Ping CHAO , Alexander KALNITSKY
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L21/76801 , H01L21/76843 , H01L21/76864 , H01L21/76865 , H01L27/016 , H01L28/24
摘要： A method of making a thin film resistor includes: forming a doped region in a semiconductor substrate; forming a dielectric layer over the substrate; forming a thin film resistor over the dielectric layer; forming a contact hole in the dielectric layer before annealing the thin film resistor, wherein the contact hole exposes a portion of the doped region; and performing rapid thermal annealing on the thin film resistor after forming the contact hole.
摘要翻译：制造薄膜电阻器的方法包括：在半导体衬底中形成掺杂区域; 在所述衬底上形成介电层; 在介电层上形成薄膜电阻; 在退火所述薄膜电阻器之前，在所述电介质层中形成接触孔，其中所述接触孔暴露所述掺杂区域的一部分; 并且在形成接触孔之后对薄膜电阻器进行快速热退火。

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