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71. 发明授权

US07890820B2 Semiconductor test system with self-inspection of memory repair analysis 有权
标题翻译：半导体测试系统具有自检内存修复分析
公开(公告)号：US07890820B2
公开(公告)日：2011-02-15
申请号：US12585016
申请日：2009-09-01
申请人： Chia-Ching Peng
发明人： Chia-Ching Peng
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/02 , G11C29/4401
摘要： A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.
摘要翻译：公开了一种具有记忆修复分析自检的半导体测试系统，包括存储器修复分析设备，分析失败存储器和自检控制器。自检控制器控制存储从外部提供的一组模拟故障位地址和一组模拟修复线地址到预先分析故障存储器中，控制存储器修复分析设备执行特定的修复分析操作到一组模拟故障位地址以产生修理线地址信息，并将计算后获得的修复线地址信息与分析失败存储器中的一组模拟维修线地址直接进行比较。因此，在物理进行测试操作之前，如果存储器修复分析装置的异常状况和其中包含的分析失败存储器，本发明能够进行自检。

72. 发明申请

US20100204949A1 Semiconductor test system with self-inspection of electrical channel 有权
标题翻译：半导体测试系统具有电气通道的自检功能
公开(公告)号：US20100204949A1
公开(公告)日：2010-08-12
申请号：US12457815
申请日：2009-06-23
申请人： Chung Lung Chang
发明人： Chung Lung Chang
IPC分类号： G01R31/02 , G06F19/00
CPC分类号： G01R31/024 , G01R31/2889 , G01R35/00
摘要： A semiconductor test system with self-inspection of an electrical channel is disclosed, which comprises a tester head, a plurality of parameter detection units and a self-inspection controller. The tester head includes a plurality of pin electronics cards inserted therein, in which the plurality of pin electronics cards contain a plurality of power channels, a plurality of I/O channels and a plurality of drive channels. The self-inspection controller outputs different inspection signals respectively to each power channel, each I/O channel and each drive channel. Then, the plurality of parameter detection units detect response signals respectively produced by each power channel, each I/O channel and each drive channel in response to the inspection signals respectively received thereby, and the response signals are judged by the self-inspection controller. Thus, the invention is capable of self-inspecting each electrical channel if it is in a normal condition, either in an open or short circuit, or if there exists a leakage condition.
摘要翻译：公开了一种具有电通道自检的半导体测试系统，其包括测试头，多个参数检测单元和自检控制器。测试器头包括插入其中的多个引脚电子卡，其中多个引脚电子卡包含多个功率通道，多个I / O通道和多个驱动通道。自检控制器分别向每个电源通道，每个I / O通道和每个驱动通道输出不同的检查信号。然后，多个参数检测单元响应于由其分别接收到的检查信号，检测由各个功率信道，每个I / O通道和每个驱动通道分别产生的响应信号，并且响应信号由自检控制器判断。因此，本发明能够在开路或短路中处于正常状态时，或者如果存在泄漏状况，则能够对每个电气通道进行自检。

73. 发明申请

US20100201392A1 Semiconductor test system with self-inspection of electrical channel for Pogo tower 有权
标题翻译：用于Pogo塔电气通道自检的半导体测试系统
公开(公告)号：US20100201392A1
公开(公告)日：2010-08-12
申请号：US12458439
申请日：2009-07-13
申请人： Chung Lung Chang
发明人： Chung Lung Chang
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R35/00 , G01R31/024 , G01R31/2889
摘要： A semiconductor test system with self-inspection of an electrical channel for a Pogo tower is disclosed, which provides a short board and closed loops are formed respectively by providing various kinds of contacts to correspondingly electrically contact various kinds of Pogo pins in the Pogo tower on a load board. A self-inspection controller outputs different inspection signals, through the above-mentioned closed loops, respectively to each power channel, each I/O channel and each drive channel, and a plurality of parameter detection units detect response signals, and the response signals are judged by the self-inspection controller. Based on it, before inspecting a wafer to be tested, the invention is capable of self-inspecting each electrical channel and each Pogo pin on the Pogo tower to see if they are respectively in a normal condition, either in an open or short circuit, or if there exists a leakage condition.
摘要翻译：公开了一种用于Pogo塔的电气通道自检的半导体测试系统，其提供短板，并且分别通过提供各种触点形成闭环，以相应地电接触Pogo塔中的各种Pogo引脚一个装载板。自检控制器通过上述闭环分别向每个电源通道，每个I / O通道和每个驱动通道输出不同的检查信号，多个参数检测单元检测响应信号，响应信号为由自检控制员判断。基于此，在检查要测试的晶片之前，本发明能够自我检查Pogo塔上的每个电气通道和每个Pogo引脚，以查看它们是否处于正常状态，无论是开路还是短路，或者如果存在泄漏状况。

74. 发明申请

US20080211527A1 Heat-resistant lens kit 失效
标题翻译：耐热镜片套件
公开(公告)号：US20080211527A1
公开(公告)日：2008-09-04
申请号：US11819083
申请日：2007-06-25
申请人： Pi-Hui Tai
发明人： Pi-Hui Tai
IPC分类号： G01R31/308
CPC分类号： G01R31/2874
摘要： A heat-resistant lens kit configured within the pogo tower of the wafer tester is disclosed. The heat-resistant lens kit has two parallel lenses and a main body with a through hole. The main body and two parallel lenses enclose a vacuum room within the through hole.
摘要翻译：公开了一种配置在晶片测试器的波峰塔内的耐热透镜套件。耐热透镜套件具有两个平行透镜和具有通孔的主体。主体和两个平行透镜在通孔内包围一个真空室。

75. 发明申请

US20070074633A1 Multi-axes inker 审中-公开
标题翻译：多轴上墨机
公开(公告)号：US20070074633A1
公开(公告)日：2007-04-05
申请号：US11296303
申请日：2005-12-08
申请人： Johnny Dai
发明人： Johnny Dai
IPC分类号： B41F17/36 , B41F17/00
CPC分类号： H01L21/67282
摘要： An inker is usually used in electrical properties testing processes to mark the defective dies of the semiconductor wafer. However, the conventional inker having only one axis will be shaken during working time, resulting in making a mistake of marking the wrong dies. The present invention discloses a multi-axes inker to fix the problem. Another axis is added to the conventional inker. The new axis can help in restricting the original axis, so that the inker is stable and can mark the right dies without a mistake.
摘要翻译：在电性能测试过程中通常使用墨水标记半导体晶片的有缺陷的裸片。然而，仅具有一个轴的常规墨水器在工作时间将被摇动，导致错误地标记错误的模具。本发明公开了一种用于解决问题的多轴上墨机。另一个轴被添加到常规的打印机。新轴可以帮助限制原始轴，从而使墨迹稳定，可以标记正确的模具，而不会出错。

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