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71. 发明授权

US07422959B2 Method for forming isolation trench in a semiconductor substrate 失效
标题翻译：在半导体衬底中形成隔离沟槽的方法
公开(公告)号：US07422959B2
公开(公告)日：2008-09-09
申请号：US11319228
申请日：2005-12-28
申请人： Woo Seok Hyun
发明人： Woo Seok Hyun
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L27/1463 , H01L27/14687 , H01L27/14689
摘要： A method for forming an isolation region in a semiconductor device such as a photodiode forms depletion layers at boundary regions between N-type regions of the photodiode and an ion injection layer in which P-type impurity ions are injected. Depletion layers are also formed between the N-type regions of the photodiode and a substrate of P-type semiconductor. Thus, depletion layers minimize a leakage current and eliminate interface defects. Low temperature processes are applied to prevent the impurity ions in the substrate from diffusing undesirably, thereby maximizing the pinning effect of the semiconductor device. The method includes steps of forming a trench region in a substrate; forming an ion injection layer by injecting impurity ions into an inner sidewall of the trench region; and forming an isolation region for a semiconductor device by filling the trench region with an undoped silicate glass film interposing the ion injection layer.
摘要翻译：在诸如光电二极管的半导体器件中形成隔离区域的方法在光电二极管的N型区域和注入有P型杂质离子的离子注入层之间的边界区域处形成耗尽层。消光层也形成在光电二极管的N型区域和P型半导体衬底之间。因此，耗尽层使漏电流最小化并消除界面缺陷。施加低温处理以防止衬底中的杂质离子不期望地扩散，从而最大化半导体器件的钉扎效应。该方法包括在衬底中形成沟槽区域的步骤; 通过将杂质离子注入到所述沟槽区域的内侧壁中而形成离子注入层; 以及通过插入所述离子注入层的未掺杂的硅酸盐玻璃膜填充所述沟槽区域来形成用于半导体器件的隔离区域。

72. 发明申请

US20080210995A1 Image sensor and method for fabricating the same 审中-公开
标题翻译：图像传感器及其制造方法
公开(公告)号：US20080210995A1
公开(公告)日：2008-09-04
申请号：US12149571
申请日：2008-05-05
申请人： Hee Sung Shim
发明人： Hee Sung Shim
IPC分类号： H01L31/0216
CPC分类号： H01L27/14689 , H01L21/28525 , H01L21/76814 , H01L27/14609 , H01L27/14636 , H01L27/14643 , H01L27/14687
摘要： An image sensor and a method for fabricating the same are disclosed, in which an impurity implantation layer having a predetermined thickness is formed on a source diffusion layer, thereby controlling a substantial contact point between a contact plug and the source diffusion layer upward from a surface of a semiconductor substrate. As a result, it is possible to minimize a length of an open hole, which is a main channel of the contact plug, so that the open hole has the sufficiently large size, thereby inducing the improvement of the contact quality between the contact plug and the source diffusion layer. Also, in case of the CMOS image sensor, in state the impurity implantation layer having the impurity selectively implanted is formed on the source diffusion layer, the impurity implantation layer is electrically connected with the source diffusion layer. Accordingly, without the additional process such as highly-impurity implantation and formation of salicide layer, it is possible for the source diffusion layer to increase the impurity concentration of impurity therein. Eventually, in case of realizing the image sensor according to the present invention, it is possible to the greatest contact quality between the contact plug and the source diffusion layer. In case of realizing the greatest contact quality between the contact plug and the source diffusion layer with the additional formation of the impurity implantation layer, for example, the source diffusion layer normally performs the function of converting the optical charges generated by the photodiode to voltage constituents. Thus, the completed image sensor according to the present invention realizes the great image quality.
摘要翻译：公开了一种图像传感器及其制造方法，其中在源极扩散层上形成具有预定厚度的杂质注入层，从而从接触插塞和源极扩散层的表面向上控制实质上的接触点的半导体衬底。结果，可以使作为接触插塞的主通道的开放孔的长度最小化，使得开孔具有足够大的尺寸，从而引起接触插塞和接触插塞之间的接触质量的提高源极扩散层。此外，在CMOS图像传感器的情况下，在源极扩散层上形成具有选择性注入的杂质的杂质注入层的状态，杂质注入层与源极扩散层电连接。因此，在没有诸如高度杂质注入和形成自对准硅化物层的附加工艺的情况下，源极扩散层可能增加杂质的杂质浓度。最终，在实现根据本发明的图像传感器的情况下，可以使接触插塞和源极扩散层之间具有最大的接触质量。在通过附加形成杂质注入层来实现接触插塞和源极扩散层之间的最大接触质量的情况下，例如，源极扩散层通常执行将由光电二极管产生的光电荷转换成电压成分的功能。因此，根据本发明的完成的图像传感器实现了良好的图像质量。

73. 发明授权

US07416937B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07416937B2
公开(公告)日：2008-08-26
申请号：US11024757
申请日：2004-12-30
申请人： Kwan Joo Koh
发明人： Kwan Joo Koh
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/10829 , H01L27/10897 , H01L27/1203 , H01L29/66181 , H01L29/945
摘要： A method creates semiconductor device in which a storage dielectric film and a storage electrode included in the capacitor is transferred from an inactive region of a semiconductor substrate to the active region thereof, i.e., into a device isolating trench such that the capacitor is prevented from unnecessarily occupying an active region of a semiconductor substrate while maintaining its proper function. In contrast to a conventional device where a capacitor is formed in the active region of the semiconductor substrate, to the capacitor is formed in the inactive region according to this process. Accordingly, the capacitor is able to maintain a trench structure without needing to perform a step of removal of a step height difference, and the active region is minimized in size. Therefore, without having a problem of a step height increase, a finished semiconductor device is able to accommodate modern demands for increased device interpretation.
摘要翻译：一种方法产生半导体器件，其中包括在电容器中的存储电介质膜和存储电极从半导体衬底的无源区转移到其有源区，即，进入器件隔离沟槽，使得不必要地防止电容器在保持其正常功能的同时占据半导体衬底的有源区。与在半导体基板的有源区域形成电容器的常规器件相反，根据该工艺，在非活性区域中形成电容器。因此，电容器能够保持沟槽结构，而不需要执行去除台阶高度差的步骤，并且有源区域的尺寸最小化。因此，没有台阶高度增加的问题，成品半导体器件能够适应现代的增加设备解读的需求。

74. 发明授权

US07407884B2 Method for forming an aluminum contact 失效
标题翻译：铝触点形成方法
公开(公告)号：US07407884B2
公开(公告)日：2008-08-05
申请号：US11319546
申请日：2005-12-29
申请人： Jae-Suk Lee
发明人： Jae-Suk Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76886 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an aluminum contact including forming a barrier metal layer on an interlayer insulation layer pattern defining a contact hole, and forming an aluminum layer on the barrier metal layer so as to fill the contact hole. The method further includes forming a photoresist pattern for ion implantation, implanting ions into the aluminum layer, and annealing by using a rapid thermal process.
摘要翻译：一种形成铝触点的方法，包括在限定接触孔的层间绝缘层图案上形成阻挡金属层，并且在阻挡金属层上形成铝层以填充接触孔。该方法还包括形成用于离子注入的光致抗蚀剂图案，将离子注入到铝层中，以及通过使用快速热处理进行退火。

75. 发明授权

US07407881B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07407881B2
公开(公告)日：2008-08-05
申请号：US11177921
申请日：2005-07-08
申请人： Han-Choon Lee
发明人： Han-Choon Lee
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/28562 , H01L21/76856 , H01L21/76862 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Enhanced step coverage and reduced resistivity of a TaSiN layer may be achieved when a semiconductor device is manufactured by: forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a contact hole that partially exposes the substrate; depositing a TaN thin film on the interlayer insulating layer and in the contact hole using a reaction gas containing a Ta precursor and a nitrogen source gas; removing impurities from the TaN thin film; forming a TaSiN thin film by reacting the impurity-removed TaN thin film with a silicon source gas, and repeating the TaN-depositing, impurity-removing, and silicon source gas-reacting steps.
摘要翻译：当通过在半导体衬底上形成层间绝缘层制造半导体器件时，可以实现TaSiN层的增强的阶梯覆盖和降低的电阻率，层间绝缘层具有部分地露出衬底的接触孔; 使用包含Ta前体和氮源气体的反应气体在层间绝缘层和接触孔中沉积TaN薄膜; 从TaN薄膜去除杂质; 通过使杂质去除的TaN薄膜与硅源气体反应，并重复TaN沉积，杂质去除和硅源气体反应步骤，形成TaSiN薄膜。

76. 发明授权

US07405437B2 CMOS image sensor and method for fabricating the same 有权
标题翻译： CMOS图像传感器及其制造方法
公开(公告)号：US07405437B2
公开(公告)日：2008-07-29
申请号：US11318577
申请日：2005-12-28
申请人： Hee Sung Shim , Tae Woo Kim
发明人： Hee Sung Shim , Tae Woo Kim
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14603 , H01L27/1463 , H01L27/14643 , H01L27/14689
摘要： A CMOS image sensor includes a first conductive type semiconductor substrate defined by a photodiode area and a transistor area, a trench formed in the semiconductor substrate corresponding to a transfer transistor of the transistor area, a gate electrode of the transfer transistor, formed in the trench, a second conductive type impurity ion area formed in the semiconductor substrate of the photodiode area, and a first conductive type impurity ion area formed on a surface of the second conductive type impurity ion area.
摘要翻译： CMOS图像传感器包括由光电二极管区域和晶体管区域限定的第一导电类型半导体衬底，形成在半导体衬底中的对应于晶体管区域的转移晶体管的沟槽，形成在沟槽中的转移晶体管的栅电极形成在所述光电二极管区域的半导体衬底中的第二导电型杂质离子区域和形成在所述第二导电型杂质离子区域的表面上的第一导电型杂质离子区域。

77. 发明授权

US07402500B2 Methods of forming shallow trench isolation structures in semiconductor devices 失效
标题翻译：在半导体器件中形成浅沟槽隔离结构的方法
公开(公告)号：US07402500B2
公开(公告)日：2008-07-22
申请号：US11181607
申请日：2005-07-13
申请人： Jae Suk Lee
发明人： Jae Suk Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/31053 , H01L21/76229
摘要： Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride layer, the first oxide layer, and the substrate in a predetermined area; forming a third oxide layer along an inside of the trench; forming a fourth oxide layer to fill up the trench; forming a sacrificial oxide layer on the fourth oxide layer; and removing the sacrificial oxide layer, the fourth oxide layer, the third oxide layer, the second oxide layer, and the nitride layer so as to form the shallow trench isolation. Thus, it is possible to minimize the damage of a narrow active area when forming an element isolation area through an STI process.
摘要翻译：公开了在半导体器件中形成浅沟槽隔离结构的方法。所公开的方法包括在基板上形成第一氧化物层，氮化物层和第二氧化物层; 通过在预定区域中蚀刻所述第二氧化物层，所述氮化物层，所述第一氧化物层和所述衬底来形成限定第一和第二有源区的沟槽; 沿着所述沟槽的内部形成第三氧化物层; 形成第四氧化物层以填充沟槽; 在所述第四氧化物层上形成牺牲氧化物层; 去除牺牲氧化物层，第四氧化物层，第三氧化物层，第二氧化物层和氮化物层，以形成浅沟槽隔离。因此，当通过STI工艺形成元件隔离区域时，可以最小化窄的有效面积的损伤。

78. 发明授权

US07402484B2 Methods for forming a field effect transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US07402484B2
公开(公告)日：2008-07-22
申请号：US10956311
申请日：2004-09-30
申请人： Hyunsoo Shin , Kyusung Kim
发明人： Hyunsoo Shin , Kyusung Kim
IPC分类号： H01L21/8238
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823814 , H01L21/823828 , H01L29/6656
摘要： Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate.
摘要翻译：公开了形成场效应晶体管的方法。所示方法包括：在衬底上形成栅电极; 以及在所述栅电极和所述衬底的至少一部分上形成氮化物层。

79. 发明授权

US07387926B2 Method for manufacturing CMOS image sensor 有权
标题翻译： CMOS图像传感器的制造方法
公开(公告)号：US07387926B2
公开(公告)日：2008-06-17
申请号：US11148212
申请日：2005-06-09
申请人： Chang Hun Han
发明人： Chang Hun Han
IPC分类号： H01L21/8238 , H01L21/00 , H01L21/302 , H01L21/469
CPC分类号： H01L27/14609 , H01L27/14689
摘要： A method for manufacturing a CMOS image sensor is provided. The method includes forming a gate electrode on a semiconductor layer having defined regions of a photodiode region and a logic region, such that a gate oxide film is interposed between the semiconductor layer and the gate electrode; forming sidewall insulating films at both sides of the gate electrode, followed by forming a salicide-preventing film over an overall surface of the gate electrode and insulating films; removing the salicide-preventing film formed in the logic region; and removing a portion of the sidewall insulating films exposed by removing the salicide-preventing film, thereby exposing an upper side surface of the gate electrode.
摘要翻译：提供了一种用于制造CMOS图像传感器的方法。该方法包括在具有光电二极管区域和逻辑区域的限定区域的半导体层上形成栅电极，使得栅极氧化膜插入在半导体层和栅电极之间; 在栅电极的两侧形成侧壁绝缘膜，然后在栅电极和绝缘膜的整个表面上形成防止防止防水膜; 去除形成在逻辑区域中的防自杀剂膜; 以及通过去除防止自杀化膜的方法去除暴露的侧壁绝缘膜的一部分，从而露出栅电极的上侧表面。

80. 发明授权

US07378319B2 Method of forming double gate dielectric layers and semiconductor device having the same 有权
标题翻译：形成双栅电介质层的方法和具有该双栅介质层的半导体器件
公开(公告)号：US07378319B2
公开(公告)日：2008-05-27
申请号：US11319531
申请日：2005-12-29
申请人： Yong Soo Ahn
发明人： Yong Soo Ahn
IPC分类号： H01L21/8234
CPC分类号： H01L29/518 , H01L21/28202 , H01L21/28211 , H01L21/823462 , H01L29/513 , H01L29/7833
摘要： A method of forming double gate dielectric layers composed of an underlying oxide layer and an overlying oxy-nitride layer is provided to prevent degradation of gate dielectric properties due to plasma-induced charges. In the method, the oxide layer is thermally grown on a silicon substrate under oxygen gas atmosphere to have a first thickness, and then the oxy-nitride layer is thermally grown on the oxide layer under nitrogen monoxide gas atmosphere to have a second thickness smaller than the first thickness. The substrate may have a high voltage area and a low voltage area, and the oxide layer may be partially etched in the low voltage area so as to have a reduced thickness. The oxy-nitride layer behaves like a barrier, blocking the inflow of the plasma-induced charges.
摘要翻译：提供了形成由下面的氧化物层和上覆的氮氧化物层构成的双栅极介电层的方法，以防止由于等离子体引起的电荷导致的栅极介电性能的劣化。在该方法中，氧化层在氧气气氛下在硅衬底上热生长以具有第一厚度，然后氮氧化物层在一氧化氮气体气氛下在氧化物层上热生长以具有小于第一厚度。衬底可以具有高电压面积和低电压面积，并且氧化物层可以在低电压区域中被部分地蚀刻以具有减小的厚度。氮氧化物层的作用就像阻挡层，阻止了等离子体引发的电荷的流入。

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