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    • 66. 发明授权
    • Image processing apparatus for detecting changes of an image signal and image processing method therefor
    • 用于检测图像信号的变化的图像处理装置及其图像处理方法
    • US06661838B2
    • 2003-12-09
    • US08651348
    • 1996-05-22
    • Shinichiro KogaYoshihiro Ishida
    • Shinichiro KogaYoshihiro Ishida
    • H04B166
    • H04N5/147G06T7/254H04N5/144H04N7/188
    • In one aspect, an image processing apparatus inputs an input image signal and detecting whether or not there is a frame change in an image by comparing the input image signal with a reference image signal. A memory is used for updating the reference image signal by storing the input image signal as the reference image signal in units of frames when there is a frame change. In another aspect, the image processing apparatus extracts change components between images by comparing the input image signal with the reference image signal, the reference image signal being an earlier input signal when a most recent prior change component was extracted. The extracted change components are corrected by detecting and removing an erroneously extracted change component, and an image change is discriminated in the input image signal on the basis of the change components as corrected.
    • 一方面,图像处理装置通过将输入图像信号与参考图像信号进行比较来输入输入图像信号并检测图像中是否存在帧变化。 当存在帧改变时,存储器通过以帧为单位存储输入图像信号作为参考图像信号来更新参考图像信号。 在另一方面,图像处理装置通过将输入图像信号与参考图像信号进行比较来提取图像之间的变化分量,当提取最近的先前变化分量时,参考图像信号是较早的输入信号。 通过检测和去除错误提取的改变分量来校正所提取的改变分量,并且基于校正的改变分量在输入图像信号中区分图像变化。
    • 67. 发明授权
    • Digital video decoding, buffering and frame-rate converting method and apparatus
    • 数字视频解码,缓冲和帧率转换方法和装置
    • US06658056B1
    • 2003-12-02
    • US09281013
    • 1999-03-30
    • Cem I. DuruözTaner OzcelikYoshinori Shimizu
    • Cem I. DuruözTaner OzcelikYoshinori Shimizu
    • H04B166
    • H04N7/01H04N19/102H04N19/152H04N19/174H04N19/176H04N19/42H04N19/423H04N19/427H04N19/44H04N19/61H04N19/85
    • A digital video presentation system is provided with a decoder to decode full frame MPEG-2 video by a single method that applies regardless of buffer memory and frame rate conversion considerations. A display control module handles frame rate and field sequence in response to host configuration, particularly buffer memory size and display type (NTSC or PAL), to host trick play command signals, and to information in the received bitstream. Pictures are decoded as buffer memory for the decoded pictures becomes available, and picture display attributes are assigned and stored in a table, one string for each decoded picture. Field display logic is informed of the to memory address of the next field to be displayed along with the attributes needed for affecting proper field display sequence, and flagging whether the memory is to be freed for use by the decoder as the field is being displayed and whether the decoder is to decode the next picture as the field is being displayed. Where memory is small, opposite field data can be output. Field sequence order is provided for output buffers in the range of from 0.53 to 0.67 frames in size, or a full frame in size. Buffer memory is optimized by maintaining tables of offset variables and accessing a fixed table of memory pointers as fields of data are being displayed. The offset data tables are identified to the display logic, which uses the data in the specified offset table to address rows of memory in which the consecutive rows of particular field to be displayed are stored. The decoder loads offset values into the offset tables as pictures are being decoded and rows of blocks of the picture are stored as memory becomes free.
    • 数字视频呈现系统具有解码器,通过采用单独的方法解码全帧MPEG-2视频,无论缓冲存储器和帧速率转换考虑如何。 显示控制模块响应于主机配置,特别是缓冲存储器大小和显示类型(NTSC或PAL)来处理帧速率和场序列,以托管特技播放命令信号以及接收到的比特流中的信息。 图像被解码为用于解码图像的缓冲存储器变得可用,并且图像显示属性被分配并存储在表中,每个解码图像是一个字符串。 通知现场显示逻辑将要显示的下一个字段的存储器地址以及影响正确的字段显示顺序所需的属性,并标记该存储器是否被释放以供解码器使用,因为该字段正在显示, 解码器是否在显示字段时对下一个图像进行解码。 在内存小的情况下,可以输出相对的场数据。 为输出缓冲区提供了大小为0.53到0.67帧的大小或整个帧的字段序列顺序。 通过在显示数据字段的同时维护偏移变量表和访问内存指针的固定表来优化缓冲存储器。 偏移数据表被识别到显示逻辑,显示逻辑使用指定的偏移表中的数据来寻址存储要显示的特定字段的连续行的存储行。 当解码图像时,解码器将偏移量加载到偏移表中,并且当存储器空闲时,存储图像的块的行。
    • 68. 发明授权
    • Digital circuit for formatting and compressing radar video data
    • 用于格式化和压缩雷达视频数据的数字电路
    • US06633613B1
    • 2003-10-14
    • US09586602
    • 2000-06-02
    • Christian L. Houlberg
    • Christian L. Houlberg
    • H04B166
    • H04N19/90
    • A digital circuit for compressing video data generated by a missile's seeker. The digital circuit includes a frame controller and a video compression engine. The frame controller generates each frame of data with each frame of data having eight subframes of one thousand eight bit words. The compression engine receives approximately sixty four scans of video data with each scan having 4000 samples of video data. The compression engine receives the first scan of video data from the missile's seeker and then writes the scan of video data to an external memory which is a static RAM. The compression engine adds each successive scan of video data to the previous scans to provide a total scan value for each sample of video data. The compression engine obtains an average value for each sample of video data by performing a binary shift. The compression engine also provides a peak value for each of the 4000 samples of video data. The frame controller then generates the eight subframes of video data with alternating bytes comprising peak video data and average video data. The frame controller also provides three bytes of frame sync, one byte of sub-frame identification and one byte representing frame count. One byte representing scan count for each subframe is generated by the compression engine.
    • 用于压缩由导弹的探测器产生的视频数据的数字电路。 数字电路包括帧控制器和视频压缩引擎。 帧控制器生成每帧数据,每帧数据具有八千位八字的八个子帧。 压缩引擎接收大约六十四个视频数据扫描,每个扫描具有4000个视频数据样本。 压缩引擎从导弹的探测器接收视频数据的第一次扫描,然后将视频数据的扫描写入作为静态RAM的外部存储器。 压缩引擎将视频数据的每个连续扫描添加到先前的扫描,以提供每个视频数据样本的总扫描值。 压缩引擎通过执行二进制移位来获得每个视频数据样本的平均值。 压缩引擎还为4000个视频数据样本中的每一个提供峰值。 帧控制器随后产生具有包括峰值视频数据和平均视频数据的交替字节的八个视频数据子帧。 帧控制器还提供三个字节的帧同步,一个字节的子帧标识和一个字节表示帧计数。 表示每个子帧的扫描计数的一个字节由压缩引擎生成。
    • 69. 发明授权
    • Apparatus and method of data reconstruction
    • 数据重建的装置和方法
    • US06618446B1
    • 2003-09-09
    • US09449635
    • 1999-11-30
    • Hayato Nakao
    • Hayato Nakao
    • H04B166
    • H04N19/42H04N19/44
    • Original data is reconstructed from an MPEG (Moving Picture Experts Group) bitstream including at least one elementary layer bitstream. The elementary layer bitstream is made of an upper layer bitstream and a plurality of lower layer bitstreams that follow the upper layer bitstream. A start code added to a header of the MPEG bitstream is detected to generate a start code detection signal. Control packets are generated when it is judged, in response to the detection signal, that the detected start code is added to the header of the upper layer bitstream. The control packets carry information on reconstruction of the original data that has been coded into the lower layer bitstreams. The lower layer bitstreams are processed according to the control packets to reconstruct the original data. The start code judgement and the control packet generation are achieved by software. On the other hand, the lower layer bitstream processing is achieved by wired-logic circuitry.
    • 从包括至少一个基本层比特流的MPEG(运动图像专家组)比特流重建原始数据。 基本层比特流由上层比特流和跟随上层比特流的多个下层比特流组成。 检测添加到MPEG比特流的头部的起始码以产生起始码检测信号。 当响应于检测信号判断检测到的起始码被添加到上层比特流的头部时,产生控制分组。 控制分组携带已经被编码为较低层比特流的原始数据的重建信息。 根据控制分组处理下层比特流以重构原始数据。 通过软件实现起始码判断和控制包生成。 另一方面,下层比特流处理通过有线逻辑电路实现。