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61. 发明授权

US09209804B2 Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same 有权
标题翻译：具有对数据输出缓冲器和具有该阻抗校准功能的半导体模块的半导体器件
公开(公告)号：US09209804B2
公开(公告)日：2015-12-08
申请号：US14524873
申请日：2014-10-27
申请人： PS4 Luxco S.A.R.L.
发明人： Kentaro Hara
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003 , H03K19/0175 , G11C29/02 , G11C29/12 , G11C29/48 , G11C11/4093 , H03K19/094 , G11C11/40 , G11C11/4076
CPC分类号： H03K19/018557 , G11C11/40 , G11C11/4076 , G11C11/4093 , G11C11/4094 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/48 , G11C2207/2254 , H01L2924/0002 , H03K19/0005 , H03K19/00315 , H03K19/017545 , H03K19/094 , H01L2924/00
摘要： A method for calibrating an output buffer including adjusting a first impedance code applied to a first plurality of first transistor units connected in parallel between a calibration terminal and a first power supply potential so that the potential on the calibration terminal substantially equals a reference potential, applying the first impedance code to a second plurality of first transistor units connected in parallel between a node and the first power supply potential, adjusting a second impedance code applied to a second transistor unit connected between the node and a second power supply potential so that the potential on the node substantially equals the reference potential, applying the first impedance code to a third plurality of first transistor units connected in parallel between a data terminal and the first power supply potential, and applying the second impedance code to a fourth plurality of second transistor units.
摘要翻译：一种用于校准输出缓冲器的方法，包括调整施加到校准端子和第一电源电位之间并联连接的第一多个第一晶体管单元的第一阻抗代码，使得校准端子上的电位基本上等于参考电位，施加所述第一阻抗代码连接到节点和所述第一电源电位之间并联连接的第二多个第一晶体管单元，调整施加到连接在所述节点和第二电源电位之间的第二晶体管单元的第二阻抗代码，使得所述电位在节点上基本上等于参考电位，将第一阻抗代码施加到并行连接在数据端和第一电源电位之间的第三多个第一晶体管单元，并将第二阻抗代码施加到第四多个第二晶体管单元。

62. 发明授权

US09148146B1 Scalable high-swing transmitter with rise and/or fall time mismatch compensation 有权
标题翻译：具有上升和/或下降时间失配补偿的可扩展高档变送器
公开(公告)号：US09148146B1
公开(公告)日：2015-09-29
申请号：US13898310
申请日：2013-05-20
申请人： PMC-Sierra, Inc.
发明人： Julien Faucher , Michael Ben Venditti
IPC分类号： H03K19/094 , H03K19/0175 , H03K19/003
CPC分类号： H03K19/00346 , H03K17/145 , H03K17/162 , H03K19/00361 , H03K19/017509
摘要： Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.
摘要翻译：公开了一种高摆幅电压模式发射机或线路驱动器。变送器可以在宽范围的电源电压下工作。增加可用的输出摆幅只是增加电源电压; 该电路适应于保持所需的输出阻抗。这允许在输出幅度和功耗之间进行权衡。所提出的架构的另一个优点是它补偿过程，电压和温度（PVT）和失配变化，以保持上升和下降时间匹配。该功能降低了使用发射机的系统中的共模噪声，从而降低了EMI。

63. 发明授权

US09130563B1 Programmable receivers and methods of implementing a programmable receiver in an integrated circuit 有权
标题翻译：可编程接收器和在集成电路中实现可编程接收器的方法
公开(公告)号：US09130563B1
公开(公告)日：2015-09-08
申请号：US14285519
申请日：2014-05-22
申请人： Xilinx, Inc.
发明人： Gautham S. Jami
IPC分类号： H03K19/094 , H03K19/0948 , H03K19/177
CPC分类号： H03K19/0948 , H03K19/17736
摘要： A programmable receiver of an integrated circuit is described. The programmable receiver comprises an input; a first programmable receiver circuit coupled to the input, wherein the first programmable receiver circuit has a first pull-up branch and a first pull-down branch and is controlled by a first enable circuit; a second programmable receiver circuit coupled to the input, wherein the second programmable receiver circuit has a second pull-up branch and a second pull-down branch and is controlled by a second enable circuit; and an output stage coupled to the first programmable receiver circuit and the second programmable receiver circuit, wherein the output stage receives an output of one of the first programmable receiver circuit and the second programmable receiver circuit. A method of implementing a programmable receiver in an integrated circuit is also disclosed.
摘要翻译：描述了集成电路的可编程接收器。可编程接收器包括输入端; 耦合到所述输入的第一可编程接收器电路，其中所述第一可编程接收器电路具有第一上拉支路和第一下拉支路，并由第一使能电路控制; 耦合到所述输入的第二可编程接收器电路，其中所述第二可编程接收器电路具有第二上拉支路和第二下拉支路，并由第二使能电路控制; 以及耦合到所述第一可编程接收器电路和所述第二可编程接收器电路的输出级，其中所述输出级接收所述第一可编程接收器电路和所述第二可编程接收器电路之一的输出。还公开了一种在集成电路中实现可编程接收器的方法。

64. 发明申请

US20150222268A1 CONFIGURABLE ANALOG FRONT ENDS FOR CIRCUITS WITH SUBSTANTIALLY GATE ENCLOSED INNER ELECTRODE MOSFET SWITCH 有权
标题翻译：具有主栅极封装的内部电极MOSFET开关的电路的可配置模拟前端
公开(公告)号：US20150222268A1
公开(公告)日：2015-08-06
申请号：US14170052
申请日：2014-01-31
申请人： Texas Instruments Deutschland GmbH
发明人： BJOERN OLIVER EVERSMANN , RALF BREDERLOW
IPC分类号： H03K19/094
CPC分类号： H03K19/09407
摘要： A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO), an analog switch having at least a first substantially gate enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain. The drain or source is a substantially gate enclosed (SGE) inner electrode relative to the gate, and the other of the source and the drain is outside the gate. The inner electrode of the first SGEFET is directly coupled to an analog bus. A switch control provides control signals to at least the gate of the first SGEFET for controlling a connectivity between the circuit module and/or the IO and the analog bus.
摘要翻译：可配置集成电路（IC）包括具有在其内部和之上形成IC的半导体表面的衬底。该IC包括至少包括一个电路模块或输入/输出（IO）的可配置的模拟前端（cAFE），具有至少第一基本上为栅极封闭的金属氧化物半导体场效应晶体管（SGEFET）的模拟开关，其具有包括栅极电介质，源极和漏极上的栅极。漏极或源极是相对于栅极的基本上栅极封闭（SGE）内部电极，源极和漏极中的另一个在栅极外部。第一SGEFET的内部电极直接耦合到模拟总线。开关控制向至少第一SGEFET的栅极提供控制信号，以控制电路模块和/或IO与模拟总线之间的连接。

65. 发明授权

US09083335B2 Semiconductor device with switch and logic circuit 有权
标题翻译：具有开关和逻辑电路的半导体器件
公开(公告)号：US09083335B2
公开(公告)日：2015-07-14
申请号：US13572951
申请日：2012-08-13
申请人： Jun Koyama
发明人： Jun Koyama
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/0944 , H03K19/017
CPC分类号： H03K19/09441 , H03K19/01714
摘要： A semiconductor device is provided, which includes a switch having a first transistor and a logic circuit having an output terminal. The logic circuit includes a bootstrap circuit having at least one second transistor. The bootstrap circuit is electrically connected to the output terminal. The first transistor and the second transistor have the same conductivity type. Each of the first transistor and the second transistor includes an oxide semiconductor layer including a channel formation region and a pair of gate electrodes with the oxide semiconductor layer provided therebetween.
摘要翻译：提供一种半导体器件，其包括具有第一晶体管和具有输出端子的逻辑电路的开关。逻辑电路包括具有至少一个第二晶体管的自举电路。引导电路电连接到输出端子。第一晶体管和第二晶体管具有相同的导电类型。第一晶体管和第二晶体管中的每一个包括包括沟道形成区域的氧化物半导体层和设置在其间的氧化物半导体层的一对栅电极。

66. 发明授权

US09082328B2 Multi-functional integrated circuit and source driver having the same 有权
标题翻译：多功能集成电路和源驱动器具有相同的功能
公开(公告)号：US09082328B2
公开(公告)日：2015-07-14
申请号：US14299734
申请日：2014-06-09
申请人： MagnaChip Semiconductor, Ltd.
发明人： Masato Nishimura
IPC分类号： G09G5/00 , G09G3/20 , H03K19/094 , G09G3/00
CPC分类号： G09G5/00 , G09G3/006 , G09G3/20 , G09G2310/027 , G09G2310/0289 , G09G2310/08 , G09G2330/04 , H03K19/094
摘要： Disclosed are a multi-functional integrated circuit and a source driver having the same. The integrated circuit (IC) chip includes: a first high-voltage transistor configured to precharge a storage node in response to a first control signal; a decoding unit configured to decode a plurality of input signals to output the decoded signal to the storage node; and a second high-voltage transistor configured to transfer an output of the decoding unit to the storage node in response to a second control signal.
摘要翻译：公开了一种多功能集成电路和具有其的源极驱动器。集成电路（IC）芯片包括：第一高电压晶体管，被配置为响应于第一控制信号对存储节点进行预充电; 解码单元，被配置为对多个输入信号进行解码以将解码信号输出到存储节点; 以及第二高电压晶体管，被配置为响应于第二控制信号将解码单元的输出传送到存储节点。

67. 发明申请

US20150091609A1 INTEGRATED CIRCUIT WITH SIGNAL ASSIST CIRCUITRY AND METHOD OF OPERATING THE CIRCUIT 有权
标题翻译：具有信号辅助电路的集成电路和操作电路的方法
公开(公告)号：US20150091609A1
公开(公告)日：2015-04-02
申请号：US14088570
申请日：2013-11-25
申请人： ARM LIMITED
发明人： Srinivasan SRINATH , Ambica ASHOK , Fakhruddin Ali BOHRA
IPC分类号： H03K19/017 , H03K19/094 , H03K19/00
CPC分类号： H03K19/01721 , G11C7/12 , G11C11/419 , H03K19/0013 , H03K19/09429 , H03K19/0963
摘要： An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following a pullup transition of the signal and provides a floating signal level following a pulldown transition, while the second assist circuit provides the floating signal level following the pullup transition and provides the logical low signal level following the pulldown transition. By providing complementary first and second assist circuits, each circuit can be optimized for the opposite transition to achieve improved performance or power consumption.
摘要翻译：集成电路具有信号辅助电路，用于帮助将信号线上的信号拉向逻辑低或高信号电平。信号辅助电路包括第一和第二辅助电路。第一辅助电路在信号的上拉转换之后将信号线耦合到逻辑高信号电平，并且在下拉转换之后提供浮动信号电平，而第二辅助电路在上拉跃迁之后提供浮动信号电平，并提供逻辑下拉转换后的低信号电平。通过提供互补的第一和第二辅助电路，每个电路可以针对相反的过渡进行优化，以实现改进的性能或功耗。

68. 发明授权

US08988106B2 Voltage mode driver with current booster (VMDCB) 有权
标题翻译：带电流增压器的电压模式驱动器（VMDCB）
公开(公告)号：US08988106B2
公开(公告)日：2015-03-24
申请号：US13917671
申请日：2013-06-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wei Chih Chen
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/0185
CPC分类号： H03K19/094 , H03K19/018521 , H03K19/018557
摘要： A voltage mode driver circuit able to achieve a larger voltage output swing than its supply voltage. The voltage mode driver circuit is supplemented by a current source or “current booster.” The circuit includes a first inverter, a second inverter, and a current source. The first inverter receives a first input and outputs a signal at a node. The second inverter receives a second input signal and outputs an inverted second input signal at the same node. The current source provides current to the node via a first switch, the first switch receiving an input at a first input where the voltage output swing at the node is larger than a power supply voltage applied to the current source. The voltage mode driver circuit uses a stable power supply voltage using a power amplifier with feedback.
摘要翻译：电压模式驱动电路能够实现比其电源电压更大的电压输出摆幅。电压模式驱动器电路由电流源或“电流升压器”补充。该电路包括第一反相器，第二反相器和电流源。第一反相器接收第一输入并输出节点处的信号。第二反相器接收第二输入信号并输出相同节点处的反相第二输入信号。电流源通过第一开关向节点提供电流，第一开关接收在节点处的电压输出摆幅大于施加到电流源的电源电压的第一输入处的输入。电压模式驱动电路使用具有反馈功率放大器的稳定电源电压。

69. 发明授权

US08922263B2 Semiconductor integrated circuit and circuit operation method 有权
标题翻译：半导体集成电路和电路操作方法
公开(公告)号：US08922263B2
公开(公告)日：2014-12-30
申请号：US12541358
申请日：2009-08-14
申请人： Hiroshi Kamizuma , Taizo Yamawaki , Yukinori Akamine , Koji Maeda
发明人： Hiroshi Kamizuma , Taizo Yamawaki , Yukinori Akamine , Koji Maeda
IPC分类号： G11C5/14 , H03K19/003 , H03K17/16 , H03K19/0175 , H03K19/094 , H03L7/00 , H03K3/00 , G06F13/42 , H04W52/02
CPC分类号： G06F1/3296 , G06F1/12 , G06F13/4243 , H04W52/0274 , Y02D10/14 , Y02D10/151 , Y02D70/00 , Y02D70/1224
摘要： The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.
摘要翻译：在输入接口处减少选择适合于抽样有效载荷数据的时钟信号的相位的数据采样单元的功耗。半导体集成电路包括输入接口和内部核心电路。输入接口包括滞后电路和数据采样单元。滞后电路将第一和第二输入阈值之间的输入信号作为睡眠命令检测。数据采样单元根据同步信号选择采样时钟信号的适当相位，并采样有效载荷数据。当检测到睡眠命令时，还向内部核心电路和数据采样单元提供睡眠信号，并将它们控制为低功耗状态。

70. 发明授权

US08922241B2 Logic circuit and semiconductor integrated circuit 有权
标题翻译：逻辑电路和半导体集成电路
公开(公告)号：US08922241B2
公开(公告)日：2014-12-30
申请号：US13610341
申请日：2012-09-11
申请人： Tatsuya Urakawa
发明人： Tatsuya Urakawa
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00369
摘要： Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal.
摘要翻译：提供了可以减小供给电源电压的变化的逻辑电路和包括该逻辑电路的半导体集成电路。逻辑电路包括缓冲单元，电压检测单元和开关单元。缓冲单元连接在第一电源或电压调节器和第二电源之间以接收电源，并将具有与输入信号相同或反相的逻辑电平的信号输出到输出端子。电压检测单元检测输出端子处的电压，并根据检测结果输出检测信号。开关单元根据检测信号将缓冲单元连接到第一电源或电压调节器。

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