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61. 发明授权

US4839850A Apparatus for bit-parallel addition of binary numbers 失效
标题翻译：二进制数位位并行加法的装置
公开(公告)号：US4839850A
公开(公告)日：1989-06-13
申请号：US883942
申请日：1986-07-10
申请人： Tobias Noll , Walter Ulbrich
发明人： Tobias Noll , Walter Ulbrich
IPC分类号： G06F7/505 , G06F7/38 , G06F7/50 , G06F7/509 , G06F7/527 , G06F7/53
CPC分类号： G06F7/509 , G06F7/5095 , G06F7/4991
摘要： In an arrangement for the bit-parallel addition of binary numbers in two's complement form, a series of adders (AD.sub.i) are provided to receive inputs for binary bits of equivalent significance and to emit intermediate sum and carry words which are combined to form result sum words. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, when the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by its carry bit.
摘要翻译：在二进制补码形式中对二进制数位进行位并行加法的方案中，提供了一系列加法器（ADi），用于接收等效有效位的二进制位的输入，并发出中和和并携带相结合的字，形成结果和话。对于溢出错误的校正，具有第二高有效性的加法器（ADn-2）的进位位被最高有效加法器（ADn-1）的进位位代替，并且当两个最高有效位的进位位加法器（ADn-1，ADn-2）不相等，最高有效加法器（ADn-1）的中间和位由其进位位代替。

62. 发明授权

US4807175A Booth's multiplier 失效
标题翻译：展位倍数
公开(公告)号：US4807175A
公开(公告)日：1989-02-21
申请号：US22968
申请日：1987-03-06
申请人： Takeji Tokumaru , Hidechika Kishigami
发明人： Takeji Tokumaru , Hidechika Kishigami
IPC分类号： G06F7/533 , G06F7/52 , G06F7/527
CPC分类号： G06F7/5338
摘要： In Booth's method of calculating a product of a multiplicand X and a multiplier Y, Y is divided into plural partial multipliers PP.sub.i (Y.sub.i, Y.sub.i+1, Y.sub.i+2); partial products PD.sub.i are formed separately in sequence by multiplying X by each of decoded partial multiplier values V.sub.pp decoded in accordance with Booth theory; and all the partial products PD.sub.i are accumulatively added to obtain the product. To increase the processing speed twice in spite of a relatively simple circuit configuration, two partial products of X and V.sub.pp are formed simultaneously in sequence and added to obtain a partial product sum PS.sub.i, and all the two partial product sums are accumulatively added to obtain a final result.
摘要翻译：在布斯计算乘法器X和乘法器Y的乘积的方法中，Y被分成多个部分乘法器PPi（Yi，Yi + 1，Yi + 2）; 通过将X乘以根据布斯理论解码的每个解码部分乘法器值Vpp，依次分别形成部分乘积PDi; 并将所有部分产品PDi累积加入以获得产品。为了使处理速度提高两倍，尽管电路结构相对简单，X和Vpp的两个部分乘积依次同时形成，并相加得到部分乘积和PSi，并且累加所有两个部分积和，以获得最后结果。

63. 发明授权

US4679165A Multiplication unit and method for the operation thereof 失效
标题翻译：乘法单元及其操作方法
公开(公告)号：US4679165A
公开(公告)日：1987-07-07
申请号：US628585
申请日：1984-07-06
申请人： Alois Rainer
发明人： Alois Rainer
IPC分类号： G06F7/53 , G06F7/52 , G06F7/527 , G06F7/54
CPC分类号： G06F7/5338
摘要： A multiplication unit for n-place binary numbers has a first register containing the multiplicand, and accumulator, and an arithmetic unit having operand inputs connected to the first register and to the accumulator. The operation to be undertaken by the arithmetic unit is to find by the bits of a multiplier which is contained in a second register, the second register being connected to an operation instruction input of the arithmetic unit. A multiplexer having inputs connected to the outputs of the second register through-connects the bits of five adjacent multiplier places to the inputs of a logic circuit, which derives the operation instruction for the arithmetic unit. The logic circuit also supplies an instruction to a mulitple shift unit interconnected between the output of the arithmetic unit and the input of the accumulator.
摘要翻译：用于n位二进制数的乘法单元具有包含被乘数和累加器的第一寄存器，以及具有连接到第一寄存器和累加器的操作数输入的算术单元。由算术单元进行的操作是通过包含在第二寄存器中的乘法器的位来查找第二寄存器，其连接到运算单元的操作指令输入。具有连接到第二寄存器的输出的输入的多路复用器通过将五个相邻乘法器位的位连接到逻辑电路的输入，该逻辑电路的输入导出运算单元的操作指令。逻辑电路还向在运算单元的输出和累加器的输入之间互连的多个移位单元提供指令。

64. 发明授权

US4547863A Integrated circuit three-input binary adder cell with high-speed sum propagation 失效
标题翻译：具有高速和和传播的集成电路三输入二进制加法器单元
公开(公告)号：US4547863A
公开(公告)日：1985-10-15
申请号：US502029
申请日：1983-06-07
申请人： Joel S. G. Colardelle
发明人： Joel S. G. Colardelle
IPC分类号： G06F7/501 , G06F7/50 , G06F7/503 , G06F7/506 , G06F7/525 , G06F7/527 , G06F
CPC分类号： G06F7/501
摘要： The binary adder cell is provided for summing three input binary variables A, B and C and has a sum output S and a carry output R. The cell comprises a first complemented exclusive-OR gate receiving the input variables A and B and providing an intermediate variable F.sub.1 =A.sym.B, a second complemented exclusive-OR gate receiving the intermediate variable F.sub.1 and the input variable C and providing the sum output S, a third complemented exclusive-OR gate receiving the input variables A and C and providing an intermediate variable F.sub.3 =A.sym.C and a carry generating circuit for generating the carry output R from the two intermediate variables F.sub.1 and F.sub.3 and the sum output S. The gates and the carry generating circuit are designed with MOS transistors according to the same general structure.
摘要翻译：二进制加法器单元被提供用于对三个输入二进制变量A，B和C求和，并且具有和输出S和进位输出R.该单元包括接收输入变量A和B的第一补码异或门，并提供中间变量F1 = A（+）B，接收中间变量F1和输入变量C并提供和输出S的第二补码异或门，接收输入变量A和C的第三补码异或门，中间变量F3 = A（+）C和用于从两个中间变量F1和F3以及和输出S产生进位输出R的进位产生电路。门和进位发生电路被设计成具有相同的MOS晶体管一般结构。

65. 发明授权

US4546446A Digital processing circuit having a multiplication function 失效
标题翻译：具有乘法功能的数字处理电路
公开(公告)号：US4546446A
公开(公告)日：1985-10-08
申请号：US352398
申请日：1982-02-25
申请人： Toshiaki Machida
发明人： Toshiaki Machida
IPC分类号： G06F7/533 , G06F7/52 , G06F7/527 , G06F7/53 , G10L19/00 , G06F7/54
CPC分类号： G06F7/5272 , G10L19/00
摘要： In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shift-register. Consecutive bits of the multiplier are applied to a Booth's decoder to produce coefficients, and the multiplicand and coefficient are multiplied by each other to produce a partial product. Partial products are produced for every three consecutive bits of the multiplier, and the obtained partial products are added to the sum of previously obtained partial products. After all the partial products are added together, the resultant sum is derived from the adder or from the feed-back path of the output from the adder.
摘要翻译：在展位的算法乘法电路中，乘法器被设置在乘法寄存器中，乘法器被设置在乘法器移位寄存器中。乘法器的连续位被应用于布斯解码器以产生系数，并且被乘数和系数被彼此相乘以产生部分乘积。对于乘法器的每三个连续位产生部分乘积，并且将获得的部分乘积加到先前获得的部分乘积的总和中。在将所有部分积加在一起之后，所得到的和从加法器或从加法器的输出的反馈路径导出。

66. 发明授权

US4533993A Multiple processing cell digital data processor 失效
标题翻译：多处理单元数字数据处理器
公开(公告)号：US4533993A
公开(公告)日：1985-08-06
申请号：US406916
申请日：1982-08-10
申请人： John V. McCanny , John G. McWhirter
发明人： John V. McCanny , John G. McWhirter
IPC分类号： G06F9/38 , G06F7/00 , G06F7/508 , G06F7/52 , G06F7/527 , G06F7/53 , G06F7/544 , G06F15/16 , G06F15/80 , G06F17/10 , G06F17/14 , G06F17/15 , G06F17/16
CPC分类号： G06F7/5306 , G06F15/8023 , G06F17/145 , G06F7/5443 , G06F2207/3836 , G06F2207/388 , G06F2207/3892 , G06F7/49994
摘要： The invention provides a digital data processor which has been systemetized down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency.Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers.Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven.
摘要翻译：本发明提供一种数字数据处理器，其被系统化到位级。处理器包括对输入位执行逻辑运算的相同处理单元的规则阵列。单元在控制数据位的输入和从单元输出的时钟的控制下重复执行单元操作。每个位在具有最高重复频率的时钟的一个重复中参与最多一个信元操作。用于处理较大数字的处理单元阵列可以从用于较小数字的较小阵列容易地构建。已经获得了一种类型的处理单元的完全工作的设计，证明了由多个单元组成的完整阵列。

67. 发明授权

US4202039A Specialized microprocessor for computing the sum of products of two complex operands 失效
标题翻译：专用微处理器，用于计算两个复杂操作数的乘积之和
公开(公告)号：US4202039A
公开(公告)日：1980-05-06
申请号：US964316
申请日：1978-11-29
申请人： Gabriel I. Epenoy , Roland Kuhne , Bernard Laurent , Philippe E. Thirion
发明人： Gabriel I. Epenoy , Roland Kuhne , Bernard Laurent , Philippe E. Thirion
IPC分类号： G06F7/53 , G06F7/48 , G06F7/506 , G06F7/508 , G06F7/527 , G06F7/533 , G06F7/544 , G06F17/16 , G06F7/52
CPC分类号： G06F7/5443 , G06F7/4812
摘要： A specialized processor capable of computing a sum of products S=.SIGMA..+-.Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j=.sqroot.-1. The processor includes an instruction storage, means for decoding instructions read out of said storage and for controlling the operation of the processor, a data storage, and a multiplication and accumulation unit which has two multiplier-accumulator devices and several buffers for storing the operands Ai, Bi, Ci and Di sequentially read out of data storage. The real part Ai and the imaginary part Bi of the multiplier are respectively applied to the Multiplier inputs of the multiplier-accumulator devices and the real part Ci of the multiplicand is applied to the Multiplicand inputs of the multiplier-accumulator devices, which simultaneously compute the products Ai Ci and Bi Ci. The imaginary part Di of the multiplicand is then applied to the Multiplicand inputs of the multiplier-accumulator devices. The first of these then computes the product Bi Di and adds the same to the product Ai Ci, while the second device computes the product Ai Di and adds the same to the product Bi Ci to simultaneously provide the real and imaginary parts of the product Pi.
摘要翻译：一种专门的处理器，能够计算乘积之和S = SIGMA +/- Pi，其中每个乘积Pi是两个n位复数操作数Ai + j Bi，乘法器和Ci + j Di，被乘数的乘积，其中j = 2ROOT -1。处理器包括指令存储装置，用于解码从所述存储器读出并用于控制处理器的操作的指令的装置，数据存储器和具有两个乘法累加器装置和多个用于存储操作数Ai的缓冲器的乘法和累加单元，Bi，Ci和Di顺序读出数据存储。乘法器的实部Ai和虚部Bi分别应用于乘法器 - 累加器器件的乘法器输入，并且被乘数的实部Ci被应用于乘法器 - 累加器器件的乘法器输入，其同时计算产品Ai Ci和Bi Ci。被乘数的虚部Di然后被施加到乘法器 - 累加器装置的乘法器输入。其中第一个然后计算产品Bi Di并将其添加到产品Ai Ci，而第二个设备计算乘积Ai Di并将其添加到产品Bi Ci以同时提供产品Pi的实部和虚部。

68. 发明授权

US4130879A Apparatus for performing floating point arithmetic operations using submultiple storage 失效
标题翻译：用于使用次数存储进行浮点算术运算的装置
公开(公告)号：US4130879A
公开(公告)日：1978-12-19
申请号：US815891
申请日：1977-07-15
申请人： David E. Cushing
发明人： David E. Cushing
IPC分类号： G06F7/487 , F02B75/02 , G06F7/508 , G06F7/52 , G06F7/527
CPC分类号： G06F7/5334 , G06F7/4876 , F02B2075/027 , G06F2207/384 , G06F2207/3844 , G06F2207/3896
摘要： A scientific processing unit includes apparatus for performing floating point multiplication operations with operands in binary coded form. The apparatus is constructed from standard multibit LSI microprocessor chips organized into a number of vertical slices. Each chip includes an arithmetic logic unit (ALU) and a random access memory (RAM). The ALU's are used to generate a predetermined number of submultiples of a mantissa portion of a floating point number which are stored in the chips memories. The submultiples are generated by multiplying the mantissa by predetermined factors which correspond to the values of multiplier digit positions selected during the multiplication operation.The apparatus further includes selection circuits which provide for selection of the least significant bit positions from each of a number of groups of multiplier digits during the multiplication operation. The least significant bit positions selected are used to read out the entire submultiple from the chip memories which thereafter are summed to produce a final product.
摘要翻译：科学处理单元包括用二进制编码形式的操作数执行浮点乘法运算的装置。该装置由组织成多个垂直切片的标准多位LSI微处理器芯片构成。每个芯片包括算术逻辑单元（ALU）和随机存取存储器（RAM）。 ALU用于产生存储在芯片存储器中的浮点数的尾数部分的预定数量的分数。通过将尾数乘以与在乘法运算期间选择的乘数数位置的值相对应的预定因子来生成子数。

69. 发明授权

US4086474A Multiplication technique in a data processing system 失效
标题翻译：数据处理系统中的乘法技术
公开(公告)号：US4086474A
公开(公告)日：1978-04-25
申请号：US728093
申请日：1976-09-30
申请人： Virendra S. Negi , Ming T. Miu
发明人： Virendra S. Negi , Ming T. Miu
IPC分类号： G06F7/53 , G06F7/508 , G06F7/52 , G06F7/527 , G06F7/54
CPC分类号： G06F7/5272
摘要： Two numbers are multiplied together without first changing either of them, if negative, to a positive number, thereby minimizing the time required in the multiplication process. In the multiplication, depending upon the sign of the multiplier and the sign of a bit in a predetermined bit location of the multiplier as shifted in a shift register, the multiplier and the multiplicand are operated on by either a shift operation or operated on by a shift and add operation.
摘要翻译：两个数字相乘在一起，而无需首先将它们中的任一个（如果为负）更改为正数，从而最小化乘法过程所需的时间。在乘法中，取决于在移位寄存器中移位的乘法器的符号和乘法器的预定位位置中的位的符号，乘法器和被乘数通过移位操作进行操作或由移位和添加操作。

70. 发明授权

US3725649A Floating point number processor for a digital computer 失效
标题翻译：浮点数字处理器数字电脑
公开(公告)号：US3725649A
公开(公告)日：1973-04-03
申请号：US3725649D
申请日：1971-10-01
申请人： RAYTHEON CO
发明人： DEERFIELD A
IPC分类号： G06F7/53 , G06F5/01 , G06F7/00 , G06F7/483 , G06F7/487 , G06F7/508 , G06F7/52 , G06F7/527 , G06F7/76 , G06F7/39 , G06F7/385
CPC分类号： G06F7/4876 , G06F7/4991 , G06F7/49936
摘要： A processor for digital numbers, specifically a multiplier using a ''''floating point'''' technique, is disclosed. The disclosed processor is adapted to determine the product of two unnormalized digital numbers, each one of such numbers being expressed as a mantissa and a signed exponent of a selected base, and to express such product as a mantissa with the greatest possible degree of significance and a signed exponent of the base. The processor is operative simultaneously to determine the sum of the exponents and the partial products of the mantissas of the numbers being processed and to normalize one of such mantissas, adjusting the sum of the exponents correspondingly. Means are also provided to stop the multiplication process as soon as all significant partial products are determined.
摘要翻译：公开了一种用于数字数字的处理器，特别是使用“浮点”技术的乘法器。所公开的处理器适于确定两个非标准化数字数字的乘积，这些数字中的每一个被表示为所选择的基数的尾数和有符号指数，并且表达这样的乘积，具有最大可能的重要性的尾数，一个签名指数的基数。处理器同时操作以确定正在处理的数字的指数和部分积的总和，并且将这些尾数之一归一化，相应地调整指数的和。还提供了一旦确定所有重要的部分产品，就停止乘法过程。

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