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61. 发明授权

US09515661B2 Circuit, semiconductor device, and clock tree 有权
标题翻译：电路，半导体器件和时钟树
公开(公告)号：US09515661B2
公开(公告)日：2016-12-06
申请号：US14705619
申请日：2015-05-06
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kiyoshi Kato
IPC分类号： H03K19/0185 , H03K19/00 , H03K3/012 , H01L29/24 , H01L29/04 , H01L27/06 , H01L27/12
CPC分类号： H03K19/018521 , H01L27/0629 , H01L27/1225 , H01L29/045 , H01L29/24 , H03K3/012 , H03K19/0008 , H03K19/0013 , H03K19/0016
摘要： A circuit with a reduced leakage current is provided. A first transistor, a third transistor, and a second transistor are electrically connected in this order in series, a drain of the second transistor and a source of the third transistor are electrically connected to each other and are electrically connected to an output node. The first transistor is a p-channel transistor. The second and third transistors are n-channel transistors each including a semiconductor region including an oxide semiconductor. The third transistor functions as a switch that controls electrical connection between a drain of the first transistor and an output node of the circuit. In the standby mode, the third transistor is in an off state.
摘要翻译：提供了具有减小的漏电流的电路。第一晶体管，第三晶体管和第二晶体管按此顺序电连接，第二晶体管的漏极和第三晶体管的源极彼此电连接并电连接到输出节点。第一晶体管是p沟道晶体管。第二和第三晶体管是n沟道晶体管，每个晶体管包括包括氧化物半导体的半导体区域。第三晶体管用作控制第一晶体管的漏极和电路的输出节点之间的电连接的开关。在待机模式下，第三晶体管处于断开状态。

62. 发明申请

US20160352336A1 DYNAMIC HIGH VOLTAGE DRIVER WITH ADJUSTABLE CLAMPED OUTPUT LEVEL 有权
标题翻译：具有可调节钳位输出电平的动态高电压驱动器
公开(公告)号：US20160352336A1
公开(公告)日：2016-12-01
申请号：US15052644
申请日：2016-02-24
申请人： International Business Machines Corporation
发明人： Gregory J. Fredeman , Abraham Mathews , Donald W. Plass , Kenneth J. Reyer
IPC分类号： H03K19/0185 , H03K5/08
CPC分类号： H03K19/018521 , H03K5/08
摘要： A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received. Processes may perform level shifting of the first voltage level to a second voltage level. The second voltage level may be clamped, for instance, but a diode circuit. The second output voltage level may be programmable, as may be current and resistance levels of the driver circuit.
摘要翻译：驱动器电路和相关技术包括管理驱动电子设备的电压。接收具有第一电压电平的输入信号。处理可以执行第一电压电平的电平移位到第二电压电平。第二电压电平可以被钳位，例如二极管电路。第二输出电压电平可以是可编程的，可以是驱动器电路的电流和电阻电平。

63. 发明授权

US09484891B2 Multi-modal communication interface 有权
标题翻译：多模态通信接口
公开(公告)号：US09484891B2
公开(公告)日：2016-11-01
申请号：US13880960
申请日：2012-01-24
申请人： Amir Amirkhany , Chaofeng Huang
发明人： Amir Amirkhany , Chaofeng Huang
IPC分类号： H03K3/01 , H01L27/02 , H03K19/003 , H03K19/0185
CPC分类号： H03K3/01 , H01L27/0251 , H03K19/00315 , H03K19/018521 , H03K19/018528
摘要： An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage.
摘要翻译：集成电路支持使用不同输入/输出（IO）电压的多种通信模式。 IC包括在低电压模式下以低IO电压工作的低压通信电路和在高电压模式下以高IO电压工作的高压通信电路。低压通信电路包括在低于高IO电压的破坏性电压下具有敏感性的关键路径中的低压晶体管。因此，低压通信电路设置有保护电路以保护低压晶体管免受高10电压的影响。

64. 发明申请

US20160308533A1 SUPPLY BOOST DEVICE 有权
标题翻译：供应升压装置
公开(公告)号：US20160308533A1
公开(公告)日：2016-10-20
申请号：US14688897
申请日：2015-04-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Ying-Yu HSU , Chien-Chun TSAI , Yu-Nan SHIH
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521
摘要： A device is disclosed that includes a driver circuit and a control circuit. The driver circuit is configured to provide an output signal according to an input signal, and operated with a first voltage and a second voltage. The driver circuit includes a pull up unit and a pull down unit configured to pull up and pull down a voltage level of the output signal, respectively. The control circuit is configured to selectively enable one of the pull up unit and the pull down unit according to the input signal, so as to adjust the voltage level of the output signal. The control circuit is further configured to drive the enabled one of the pull up unit and the pull down unit in a voltage mode or a current mode selectively according to the voltage level of the output signal, the first voltage and the second voltage.
摘要翻译：公开了一种包括驱动电路和控制电路的装置。驱动器电路被配置为根据输入信号提供输出信号，并且以第一电压和第二电压进行操作。驱动器电路包括分别上拉和下拉输出信号电压电平的上拉单元和下拉单元。控制电路被配置为根据输入信号选择性地使能上拉单元和下拉单元中的一个，以便调节输出信号的电压电平。控制电路还被配置为根据输出信号的电压电平，第一电压和第二电压选择性地以电压模式或电流模式驱动上拉单元和下拉单元中的使能的一个。

65. 发明申请

US20160308518A1 SIGNAL POTENTIAL CONVERTER 有权
标题翻译：信号电位转换器
公开(公告)号：US20160308518A1
公开(公告)日：2016-10-20
申请号：US15191455
申请日：2016-06-23
申请人： SOCIONEXT INC.
发明人： Seiji WATANABE
IPC分类号： H03K5/08 , H03K3/356
CPC分类号： H03K5/08 , H03K19/017581 , H03K19/0185 , H03K19/018521
摘要： In a signal potential converter, a capacitor receives an input signal CIN at one terminal thereof and has the other terminal thereof connected to a terminal node. A clamp circuit defines a potential (signal IN) at the terminal node within the range of a first potential to a second potential. The clamp circuit includes a level adjuster circuit configured to adjust at least one of the first and second potentials according to a supply voltage of a circuit that drives the input signal CIN.
摘要翻译：在信号电位转换器中，电容器在其一个端子处接收输入信号CIN，并且其另一端连接到终端节点。钳位电路在第一电位到第二电位的范围内定义终端节点处的电位（信号IN）。钳位电路包括电平调节器电路，其被配置为根据驱动输入信号CIN的电路的电源电压来调节第一和第二电位中的至少一个。

66. 发明申请

US20160301394A1 SINGLE WIRE INTERFACE 有权
标题翻译：单线接口
公开(公告)号：US20160301394A1
公开(公告)日：2016-10-13
申请号：US14684594
申请日：2015-04-13
申请人： INFINEON TECHNOLOGIES AG
发明人： Thomas Leutgeb , Walter Kargl , Helmut Koroschetz
IPC分类号： H03K3/3568
CPC分类号： H03K19/09429 , H03K19/018521
摘要： A system including a first device having a push-pull circuit configured to transmit a synchronization symbol; and a second device coupled to the first device by a single wire interface, and configured to, in response to receiving the synchronization symbol, transmit a data symbol to the first device while the push-pull circuit is in a tristate phase.
摘要翻译：一种系统，包括：第一设备，具有被配置为发送同步符号的推挽电路; 以及第二设备，其通过单线接口耦合到第一设备，并且被配置为响应于接收到同步符号，在推挽电路处于三态阶段期间将数据符号发送到第一设备。

67. 发明申请

US20160226493A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE REGARDING THE DETECTION OF DEGRADATION 有权
标题翻译：关于降解检测的半导体集成电路设备
公开(公告)号：US20160226493A1
公开(公告)日：2016-08-04
申请号：US15040817
申请日：2016-02-10
申请人： SK hynix Inc.
发明人： Jeong Tae HWANG , Jin Youp CHA , Young Sik HEO
IPC分类号： H03K19/0185 , G01R31/28 , H03K17/687
CPC分类号： H03K19/018521 , G01R31/2856 , H03K17/102
摘要： A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.
摘要翻译：半导体集成电路器件可以包括目标PMOS晶体管，目标NMOS晶体管，第一应力施加电路，第二应力施加电路，第三应力施加电路和第四应力施加电路。反相器可以包括目标PMOS晶体管和NMOS晶体管。第一应力施加电路可以被配置为将第一DC电平施加到目标PMOS晶体管的栅极。第二应力施加电路可以被配置为将第二DC电平施加到目标NMOS晶体管的栅极。第三应力施加电路可以被配置为向目标NMOS晶体管的栅极施加AC电压形状。第四应力施加电路可以被配置为将AC电压施加到目标NMOS晶体管的漏极。

68. 发明授权

US09407242B2 Voltage level shifter for high voltage applications 有权
标题翻译：用于高压应用的电压电平转换器
公开(公告)号：US09407242B2
公开(公告)日：2016-08-02
申请号：US14743828
申请日：2015-06-18
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Liang Qiu , Wenzhong Zhang
IPC分类号： H03K3/00 , H03K3/356
CPC分类号： H03K3/356 , H03K3/356113 , H03K19/018521
摘要： A voltage level shifter for high voltage applications has a low voltage domain current mirror having first and second branches. A high voltage switch and a resistor are connected in series with the second branch. An output stage provides an output signal that is a function of a voltage difference across the resistor, and the output stage and the resistor are in the high voltage domain. Assertion of an input signal in the low voltage domain develops a first current in the first branch, and causes the high voltage switch to pass in the resistor a second current from the second branch that is a function of the first current and develops the voltage difference across the resistor. Only the high voltage switch needs to have high breakdown voltage characteristics.
摘要翻译：用于高电压应用的电压电平转换器具有具有第一和第二分支的低电压域电流镜。高压开关和电阻与第二支路串联。输出级提供作为电阻器两端的电压差的函数的输出信号，并且输出级和电阻器处于高电压域。在低电压域中输入信号的断言在第一分支中形成第一电流，并且使得高压开关从第二分支传递电阻器到第二电流的第二电流，该第二分支是第一电流的函数，并且产生电压差跨过电阻只有高压开关需要具有较高的击穿电压特性。

69. 发明申请

US20160218753A1 SERIALIZING TRANSMITTER 有权
标题翻译：串行发送器
公开(公告)号：US20160218753A1
公开(公告)日：2016-07-28
申请号：US14604643
申请日：2015-01-23
申请人： Microsoft Technology Licensing, LLC
发明人： Alan S. Fiedler
IPC分类号： H04B1/04
CPC分类号： H04B1/04 , H03K19/0005 , H03K19/018521 , H04B1/0057
摘要： In embodiments of a serializing transmitter, the serializing transmitter includes N multiplexing drive units, each configured to generate a series of output pulses derived from input data signals and multi-phase clock signals, and each multiplexing drive unit including a pulse-controlled push-pull output driver having first and second inputs and an output. Each multiplexing driver unit further includes a first M:1 pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, wherein each of the first and second M:1 pulse-generating multiplexers has four or fewer clock inputs.
摘要翻译：在串行发射机的实施例中，串行发射机包括N个复用驱动单元，每个复用驱动单元被配置为产生从输入数据信号和多相时钟信号导出的一系列输出脉冲，并且每个复用驱动单元包括脉冲控制的推挽输出驱动器具有第一和第二输入和输出。每个复用驱动器单元还包括具有耦合到脉冲控制的推挽输出驱动器的第一输入的输出的第一M：1脉冲产生多路复用器和第二M：1脉冲产生多路复用器，其输出耦合到脉冲控制推挽输出驱动器的第二输入，其中第一和第二M：1脉冲发生多路复用器中的每一个具有四个或更少的时钟输入。

70. 发明授权

US09391619B2 Level-shift circuits compatible with multiple supply voltage 有权
标题翻译：电平转换电路与多电源电压兼容
公开(公告)号：US09391619B2
公开(公告)日：2016-07-12
申请号：US14326747
申请日：2014-07-09
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Qiang Si , Cheng Liu
IPC分类号： H03K3/00 , H03K19/0175
CPC分类号： H03K17/08122 , H03K19/0175 , H03K19/018521
摘要： A level-shift circuit, receiving a supply voltage and a input signal, includes a pre-stage voltage conversion circuit and a post-stage voltage conversion circuit. The pre-stage voltage conversion circuit includes a first voltage protection module generating an inner conversion voltage and a first voltage conversion module converting the input signal into a pre-stage output signal according to the inner conversion voltage. The post-stage voltage conversion circuit includes a second voltage protection module generating a first inverse output signal, a first output signal, a second inverse output signal, and a second output signal. The transistors of the pre-stage voltage conversion circuit and the post-stage voltage conversion circuit have a punch-through voltage. The level-shift makes the stress of the transistors less than the punch-through voltage when the supply voltage is greater than the punch-through voltage, and remains the driving capability when being less than the punch-through voltage.
摘要翻译：接收电源电压和输入信号的电平移位电路包括前级电压转换电路和后级电压转换电路。前级电压转换电路包括产生内部转换电压的第一电压保护模块和根据内部转换电压将输入信号转换成前级输出信号的第一电压转换模块。后级电压转换电路包括产生第一反相输出信号，第一输出信号，第二反相输出信号和第二输出信号的第二电压保护模块。前级电压转换电路和后级电压转换电路的晶体管具有穿通电压。当电源电压大于穿通电压时，电平漂移使得晶体管的应力小于穿通电压，并且当小于穿通电压时，其保持驱动能力。

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