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61. 发明授权

US07550359B1 Methods involving silicon-on-insulator trench memory with implanted plate 有权
标题翻译：涉及具有植入板的绝缘体上硅沟槽存储器的方法
公开(公告)号：US07550359B1
公开(公告)日：2009-06-23
申请号：US12116626
申请日：2008-05-07
申请人： Kangguo Cheng , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions into the substrate and the SOI layer on a first opposing side of the trench and a second opposing side the trench to partially form a capacitor, depositing a node dielectric in the trench, filling the trench with a first polysilicon, removing a portion of the first polysilicon from the trench, removing an exposed portion of the node dielectric, filling the trench with a second polysilicon, masking to define an active region on the hardmask layer, forming shallow trench isolation (STI) such that the STI contacts a portion of the buried oxide layer, removing the hardmask layer, and forming a transistor.
摘要翻译：一种用于制造绝缘体上硅（SOI）沟槽存储器的方法，包括在衬底上形成沟槽，其中掩埋氧化物层设置在衬底上，SOI层设置在掩埋氧化物层上，并且设置硬掩模层在所述SOI层上，将离子注入到所述衬底中并且在所述沟槽的第一相对侧上的所述SOI层和所述沟槽的第二相对侧，以部分地形成电容器，在所述沟槽中沉积节点电介质，用第一多晶硅填充所述沟槽从所述沟槽去除所述第一多晶硅的一部分，去除所述节点电介质的暴露部分，用第二多晶硅填充所述沟槽，以掩蔽以限定所述硬掩模层上的有源区域，形成浅沟槽隔离（STI），使得 STI接触掩埋氧化物层的一部分，去除硬掩模层，并形成晶体管。

62. 发明授权

US07537915B2 Nucleic acids encoding chromophores/fluorophores and methods for using the same 有权
标题翻译：编码发色团/荧光团的核酸及其使用方法
公开(公告)号：US07537915B2
公开(公告)日：2009-05-26
申请号：US11607313
申请日：2006-11-30
申请人： Sergey A. Lukyanov , Arcady F. Fradkov , Yulii A. Labas , Mikhail V. Matz , Alexey Terskikh
发明人： Sergey A. Lukyanov , Arcady F. Fradkov , Yulii A. Labas , Mikhail V. Matz , Alexey Terskikh
IPC分类号： C12P21/06
CPC分类号： H01L27/1087 , C07K14/43504 , C07K14/43595 , C07K2319/60 , H01L21/3144 , H01L21/31604 , H01L29/66181
摘要： Nucleic acid compositions encoding novel chromo/fluoroproteins and mutants thereof are provided. The subject proteins of interest are proteins that are colored and/or fluorescent, where this feature arises from the interaction of two or more residues of the protein. The subject proteins are further characterized in that they are either obtained from non-bioluminescent Cnidarian, e.g., Anthozoan, species or are obtained from non-Pennatulacean (sea pen) species. Specific proteins of interest include proteins obtained from the following specific Anthozoan species: Anemonia majano (NFP-1), Clavularia sp. (NFP-2), Zoanthus sp. (NFP-3 & NFP-4), Discosoma striata (NFP-5), Discosoma sp. “red”(NFP-6), Anemonia sulcata (NFP-7), Discosoma sp “green”(NFP-8), and Discosoma sp.“magenta”(NFP-9). Also of interest are proteins that are substantially similar to, or mutants of, the above specific proteins. Also provided are fragments of the nucleic acids and the peptides encoded thereby, as well as antibodies to the subject proteins and transgenic cells and organisms. The subject protein and nucleic acid compositions find use in a variety of different applications. Finally, kits for use in such applications, e.g., that include the subject nucleic acid compositions, are provided.
摘要翻译：提供了编码新色氨酸/荧光素蛋白的核酸组合物及其突变体。感兴趣的主题蛋白质是着色和/或荧光的蛋白质，其中该特征来自蛋白质的两个或多个残基的相互作用。主题蛋白的进一步特征在于它们是从非生物发光的Cnidarian（例如Anthozoan）物种获得的，或者是从非藜芦烷（海洋笔）物种获得的。感兴趣的特异性蛋白质包括从以下特异性Anthozoan物种获得的蛋白质：Anemonia majano（NFP-1），Clavularia sp。（NFP-2），Zoanthus sp。（NFP-3和NFP-4），脊髓细胞瘤（NFP-5），Discosoma sp。（NFP-6），NFP-7（NFP-7），Discosoma sp“green”（NFP-8）和Discosoma sp。“洋红”（NFP-9）。还感兴趣的是与上述特定蛋白质基本相似或突变体的蛋白质。还提供了核酸的片段和由其编码的肽，以及针对受试者蛋白质和转基因细胞和生物体的抗体。主题蛋白质和核酸组合物可用于各种不同的应用。最后，提供了用于此类应用的试剂盒，例如包括本发明的核酸组合物。

63. 发明授权

US07531406B2 Method for fabricating an electrical component 有权
标题翻译：电气部件的制造方法
公开(公告)号：US07531406B2
公开(公告)日：2009-05-12
申请号：US11399811
申请日：2006-04-07
申请人： Alejandro Avellan , Thomas Hecht , Stefan Jakschik , Uwe Schroeder
发明人： Alejandro Avellan , Thomas Hecht , Stefan Jakschik , Uwe Schroeder
IPC分类号： H01L21/8234
CPC分类号： H01L28/65 , H01L27/1087 , H01L29/66181
摘要： An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.
摘要翻译：制造诸如DRAM半导体存储器或场效应晶体管的电气部件。制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

64. 发明申请

US20090079027A1 SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM 有权
标题翻译：与SOI嵌入式DRAM兼容的稳定隔离结构
公开(公告)号：US20090079027A1
公开(公告)日：2009-03-26
申请号：US11861614
申请日：2007-09-26
申请人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
发明人： Kangguo Cheng , Munir D. Naeem , David M. Dobuzinsky , Byeong Y. Kim
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203
摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.
摘要翻译：在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。在深沟槽中形成导电沟槽填充区域。施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

65. 发明申请

US20090057574A1 METHODS FOR MODIFYING FEATURES OF A WORKPIECE USING A GAS CLUSTER ION BEAM 有权
标题翻译：使用气体离子束修饰工件特征的方法
公开(公告)号：US20090057574A1
公开(公告)日：2009-03-05
申请号：US11850423
申请日：2007-09-05
申请人： Reinhard Wagner , Wesley Skinner
发明人： Reinhard Wagner , Wesley Skinner
IPC分类号： G21K5/04
CPC分类号： H01J37/3053 , H01J37/302 , H01J2237/0812 , H01J2237/30461 , H01L21/2633 , H01L21/28123 , H01L21/3065 , H01L22/12 , H01L22/14 , H01L22/20 , H01L27/1087 , H01L29/66181
摘要： Embodiments of methods of modifying surface features on a workpiece with a gas cluster ion beam are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述使用气体簇离子束改变工件上的表面特征的方法的实施例。可以描述和要求保护其他实施例。

66. 发明申请

US20080265299A1 Strained channel dynamic random access memory devices 有权
标题翻译：应变通道动态随机存取存储器件
公开(公告)号：US20080265299A1
公开(公告)日：2008-10-30
申请号：US12167828
申请日：2008-07-03
申请人： Mayank Bulsara , Matthew T. Currie , Anthony J. Lochtefeld
发明人： Mayank Bulsara , Matthew T. Currie , Anthony J. Lochtefeld
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L28/40 , H01L29/1054 , H01L29/7849 , H01L29/945
摘要： DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
摘要翻译：尤其是通过将导电材料沉积到沟槽中或掺杂限定沟槽的半导体区域形成的DRAM沟槽电容器。

67. 发明授权

US07439559B2 SOI device with different crystallographic orientations 有权
标题翻译：具有不同晶体取向的SOI器件
公开(公告)号：US07439559B2
公开(公告)日：2008-10-21
申请号：US11469039
申请日：2006-08-31
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/74
CPC分类号： H01L29/78642 , H01L27/10864 , H01L27/1087
摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.
摘要翻译：在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。

68. 发明申请

US20080246068A1 TRENCH CAPACITORS AND MEMORY CELLS USING TRENCH CAPACITORS 有权
标题翻译：使用TRENCH电容器的TRENCH电容器和存储器电池
公开(公告)号：US20080246068A1
公开(公告)日：2008-10-09
申请号：US12138536
申请日：2008-06-13
申请人： Kangguo Cheng , Xi Li
发明人： Kangguo Cheng , Xi Li
IPC分类号： H01L29/94
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/1087
摘要： A trench structure, a method of forming the trench structure, a memory cell using the trench structure and a method of forming a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.
摘要翻译：沟槽结构，形成沟槽结构的方法，使用沟槽结构的存储单元以及使用沟槽结构形成存储单元的方法。沟槽结构包括：衬底; 具有连续的上，中和下区域的沟槽，所述沟槽从所述衬底的顶表面延伸到所述衬底中; 所述沟槽的上部区域具有垂直侧壁轮廓; 并且沟槽的中间区域具有锥形侧壁轮廓。

69. 发明申请

US20080220575A1 METHOD OF FABRICATING DYNAMIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：制作动态随机存取存储器的方法
公开(公告)号：US20080220575A1
公开(公告)日：2008-09-11
申请号：US12126942
申请日：2008-05-26
申请人： Yi-Nan Su
发明人： Yi-Nan Su
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： A method of fabricating a dynamic random access memory is provided. A trench capacitor is formed in a substrate and an isolation structure is formed on the trench capacitor. A gate structure and a passing gate structure are formed on the substrate. The gate structure is on one side of the passing gate structure. A source region and a drain region are formed in the substrate on both sides of the gate structure. A dielectric layer is formed on the substrate. A contact is formed in the dielectric layer and the isolation structure, at the other side of the passing gate structure, and is coupled to the trench capacitor. Since the contact is formed at the other side of the passing gate structure, the contact would not coupled to the source and drain regions when misalignment occurs.
摘要翻译：提供一种制造动态随机存取存储器的方法。在衬底中形成沟槽电容器，并且在沟槽电容器上形成隔离结构。在基板上形成栅极结构和通过栅极结构。栅极结构位于通过栅极结构的一侧。源极区域和漏极区域形成在栅极结构的两侧的基板中。在基板上形成电介质层。在通路栅极结构的另一侧，在电介质层和隔离结构中形成接触，并且与沟槽电容器耦合。由于接触形成在通过栅极结构的另一侧，所以当发生不对准时，接触不会耦合到源极和漏极区。

70. 发明授权

US07414278B2 Semiconductor device with shallow trench isolation which controls mechanical stresses 有权
标题翻译：具有浅沟槽隔离的半导体器件，其控制机械应力
公开(公告)号：US07414278B2
公开(公告)日：2008-08-19
申请号：US11017828
申请日：2004-12-22
申请人： Shinji Sugatani , Koichi Hashimoto , Yoshihiro Takao
发明人： Shinji Sugatani , Koichi Hashimoto , Yoshihiro Takao
IPC分类号： H01L27/108
CPC分类号： H01L27/1087 , H01L21/76229 , H01L27/0629 , H01L27/10829 , H01L29/66181 , H01L29/945
摘要： The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; a device isolation film 32b buried in the bottom of the trench 16b; and a capacitor formed on a side wall of an upper part of the second trench 16b and including an impurity diffused region 40 as a first electrode, a capacitor dielectric film 43 of a silicon oxide-based insulating film and a second electrode 46.
摘要翻译：半导体器件包括具有沟槽16a和形成在其中的沟槽16b的半导体衬底10; 掩埋在沟槽16a中的器件隔离膜32a，其包括含有氮化硅膜20和氧化硅类绝缘材料的绝缘膜28的衬垫膜; 掩埋在沟槽16b的底部的器件隔离膜32b; 以及形成在第二沟槽16b的上部的侧壁上并且包括作为第一电极的杂质扩散区域40，氧化硅类绝缘膜的电容器电介质膜43和第二电极46的电容器。

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