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61. 发明申请

US20150333058A1 Semiconductor Device in a Semiconductor Substrate and Method of Manufacturing a Semiconductor Device in a Semiconductor Substrate 有权
标题翻译：半导体基板中的半导体器件和半导体基板中的半导体器件的制造方法
公开(公告)号：US20150333058A1
公开(公告)日：2015-11-19
申请号：US14813738
申请日：2015-07-30
申请人： Infineon Technologies AG
发明人： Andreas Meiser , Markus Zundel , Till Schloesser
IPC分类号： H01L27/08 , H01L21/768 , H01L29/40 , H01L49/02
CPC分类号： H01L27/0805 , H01L21/7687 , H01L21/76877 , H01L27/0629 , H01L28/40 , H01L28/60 , H01L28/90 , H01L29/407
摘要： A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench portion extending in a first direction and a second trench portion extending in the first direction. The first trench portion is connected with the second trench portion in a lateral direction. The first trench portion and the second trench portion are arranged one after the other along the first direction. The semiconductor device further includes a trench conductive structure having a conductive material disposed in the first trench portion, and a trench capacitor structure having a capacitor dielectric and a first capacitor electrode disposed in the second trench portion. The first capacitor electrode includes a layer lining a sidewall of the second trench portion.
摘要翻译：半导体衬底中的半导体器件包括在半导体衬底的第一主表面中的沟槽。沟槽包括沿第一方向延伸的第一沟槽部分和沿第一方向延伸的第二沟槽部分。第一沟槽部分沿横向方向与第二沟槽部分连接。第一沟槽部分和第二沟槽部分沿着第一方向一个接一个布置。半导体器件还包括具有设置在第一沟槽部分中的导电材料的沟槽导电结构，以及具有电容器电介质的沟槽电容器结构和设置在第二沟槽部分中的第一电容器电极。第一电容器电极包括衬在第二沟槽部分的侧壁上的层。

62. 发明申请

US20150318407A1 Adding Decoupling Function for TAP Cells 审中-公开
标题翻译：添加TAP单元的去耦功能
公开(公告)号：US20150318407A1
公开(公告)日：2015-11-05
申请号：US14797614
申请日：2015-07-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Ji Chen , Li-Chun Tien
IPC分类号： H01L29/94 , H01L23/528 , H01L29/10 , H01L27/08
CPC分类号： H01L29/94 , H01L23/528 , H01L27/0805 , H01L27/0808 , H01L29/107 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： A circuit includes a tap cell. The tap cell includes a well region, a first well pickup region in the well region, a VDD power rail and a VSS power rail spaced apart from the VDD power rail. The tap cell also includes a first jog extending from the VDD power rail toward the VSS power rail and forming a continuous region with the VDD power rail. The tap cell further comprises a first capacitor including a first gate electrode line acting as a first capacitor plate, and the first well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is overlapped by and connected to the first jog, and a second one of the first and second capacitor plates is coupled to the VSS power rail.
摘要翻译：电路包括抽头单元。抽头单元包括阱区，阱区中的第一阱拾取区，VDD电源轨和与VDD电源轨分开的VSS电源轨。分接单元还包括从VDD电源轨向VSS电源轨延伸的第一点动，并且与VDD电源轨形成连续区域。抽头单元还包括第一电容器，其包括用作第一电容器板的第一栅电极线和用作第二电容器板的一部分的第一阱拾取区。第一和第二电容器板中的第一电容器板与第一点动器重叠并连接到第一和第二电容器板，第二和第二电容器板中的第二个耦合到VSS电源轨。

63. 发明授权

US09153639B2 Memory devices with vertical storage node bracing and methods of fabricating the same 有权
标题翻译：具有垂直存储节点支撑的存储器件及其制造方法
公开(公告)号：US09153639B2
公开(公告)日：2015-10-06
申请号：US13764243
申请日：2013-02-11
申请人： Samsung Electronics Co., Ltd.
发明人： Junghwan Lee
IPC分类号： H01L49/02 , H01L27/08 , H01L27/108
CPC分类号： H01L28/40 , H01L27/0805 , H01L27/10808 , H01L27/10852 , H01L28/91
摘要： A memory device includes a substrate and a plurality of vertical storage nodes linearly spaced apart on the substrate along a first direction. The device further includes at least one support pattern abutting sidewalls of the storage nodes, the at least one support pattern having portions that bridge first pairs of adjacent ones of the storage nodes and openings therein that separate second pairs of adjacent ones of the storage nodes. First distances between the storage nodes of the respective first pairs may be greater than second distances between the storage nodes of the respective second pairs. Methods of fabricating such devices are also described.
摘要翻译：存储器件包括衬底和沿着第一方向在衬底上线性间隔开的多个垂直存储节点。所述装置还包括邻接所述存储节点的侧壁的至少一个支撑图案，所述至少一个支撑图案具有跨越所述存储节点中的第一对相邻存储节点和开口的部分，所述第一对存储节点中的开口与所述存储节点中相邻的第二对存储节点分开。各个第一对的存储节点之间的第一距离可以大于相应的第二对的存储节点之间的第二距离。还描述了制造这种装置的方法。

64. 发明授权

US09147688B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09147688B2
公开(公告)日：2015-09-29
申请号：US14579394
申请日：2014-12-22
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Hitoshi Saito
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00 , H01L27/115 , H01L49/02 , H01L27/108
CPC分类号： H01L27/11502 , H01L27/0805 , H01L27/108 , H01L27/11507 , H01L27/11509 , H01L28/56 , H01L28/60
摘要： An embodiment of a compound semiconductor device includes: a first lower electrode; a first insulating film over the first lower electrode; a first upper electrode over the first insulating film; a second lower electrode separate from the first lower electrode; a second insulating film over the second lower electrode; a third insulating film over the second insulating film; and a second upper electrode over on the third insulating film. A thickness of the first insulating film is substantially the same as a thickness of the third insulating film, a contour of the third insulating film in planar view is outside a contour of the second insulating film in planar view, and a contour of the second upper electrode in planar view is inside the contour of the second insulating film in planar view.
摘要翻译：化合物半导体器件的实施例包括：第一下电极; 第一下电极上的第一绝缘膜; 在所述第一绝缘膜上方的第一上电极; 与第一下电极分离的第二下电极; 在所述第二下电极上的第二绝缘膜; 第二绝缘膜上的第三绝缘膜; 以及位于第三绝缘膜上的第二上电极。第一绝缘膜的厚度与第三绝缘膜的厚度基本相同，平面图中的第三绝缘膜的轮廓在平面图中位于第二绝缘膜的轮廓之外，第二上部的轮廓平面图中的电极在平面图中位于第二绝缘膜的轮廓内。

65. 发明申请

US20150249081A1 DIRECTIONAL FINFET CAPACITOR STRUCTURES 有权
标题翻译：方向FINFET电容器结构
公开(公告)号：US20150249081A1
公开(公告)日：2015-09-03
申请号：US14498322
申请日：2014-09-26
申请人： QUALCOMM Incorporated
发明人： Hong CHUN
IPC分类号： H01L27/06 , H01L49/02 , H01L23/522 , H01L29/78
CPC分类号： H01L27/0629 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L28/86 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a capacitor within a FinFET device includes patterning a first gate interconnect material having a first recess. The method also includes patterning a first trench interconnect material coupled to the first gate interconnect material at the first recess to form a first plate of a FinFET capacitive structure.
摘要翻译：在FinFET器件内制造电容器的方法包括对具有第一凹槽的第一栅极互连材料进行构图。该方法还包括图案化在第一凹槽处耦合到第一栅极互连材料的第一沟槽互连材料，以形成FinFET电容结构的第一板。

66. 发明授权

US09117796B2 Semiconductor arrangement and formation thereof 有权
标题翻译：半导体装置及其形成
公开(公告)号：US09117796B2
公开(公告)日：2015-08-25
申请号：US14166925
申请日：2014-01-29
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Bo-Jr Huang , Nan-Hsin Tseng , Ping-Han Tsai , Wei-Hao Kao
IPC分类号： H01L21/8242 , H01L49/02 , H01L23/522 , H01L27/02 , H01L27/06 , H01L21/768 , H01L27/08
CPC分类号： H01L27/0805 , H01L23/5223 , H01L23/5226 , H01L27/0688 , H01L28/60 , H01L2224/18 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor arrangement and methods of forming the same are described. A semiconductor arrangement includes a first tier including a first capacitor, a second tier over the first tier, the second tier including a second capacitor, and a first substrate between the first tier and the second tier. The first capacitor is connected to the second capacitor through the substrate. A plurality of tiers are contemplated, such that a total capacitance of the semiconductor arrangement increases based upon interconnection of metal layers of different tiers. Additionally, the semiconductor arrangement has a greater area efficiency as compared to multiple capacitors in parallel.
摘要翻译：对半导体装置及其形成方法进行说明。半导体装置包括第一层，包括第一电容器，第一层上的第二层，第二层包括第二电容器，以及在第一层和第二层之间的第一衬底。第一电容器通过衬底连接到第二电容器。考虑多层，使得半导体布置的总电容基于不同层的金属层的互连而增加。此外，与并联的多个电容器相比，半导体布置具有更大的面积效率。

67. 发明申请

US20150221716A1 METAL-INSULATOR-METAL CAPACITOR STRUCTURES 有权
标题翻译：金属绝缘体 - 金属电容器结构
公开(公告)号：US20150221716A1
公开(公告)日：2015-08-06
申请号：US14688807
申请日：2015-04-16
申请人： QUALCOMM, Incorporated
发明人： Renatas Jakushokas , Vaishnav Srinivas , Robert Won Chol Kim
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01G4/002 , H01G4/005 , H01G4/33 , H01G4/385 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/87 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.
摘要翻译：本文描述了能够提供低电压电容器和高压电容器的电容器结构。在一个实施例中，电容器结构包括由第一金属层形成的第一电极，由第二金属层形成的第二电极和由第三金属层形成的第三电极，其中第二和第三电极间隔比第第一和第二电极。电容器结构还包括在第一和第二电极之间的第一电介质层和在第二和第三金属层之间的第二电介质层，其中第二电介质层具有比第一电介质层更大的厚度。第一电极耦合到第一电源轨，第三电极耦合到第二电源轨，并且第二电源轨具有比第一电源轨更高的电源电压。

68. 发明申请

US20150221713A1 VOLTAGE AND TEMPERATURE INDEPENDENT MIM CAPACITORS 有权
标题翻译：电压和温度独立的MIM电容器
公开(公告)号：US20150221713A1
公开(公告)日：2015-08-06
申请号：US14170151
申请日：2014-01-31
申请人： WaferTech, LLC
发明人： Hsin-l LI , Wen-Bin Tsai , Kin Fung Lam
IPC分类号： H01L49/02 , H01L23/34 , H01L23/522
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： MIM capacitors that are temperature and/or voltage independent, and a methodology for formulating the MIM capacitors for use in semiconductor integrated circuits, is provided. Vertical MIM capacitive structures include at least two vertically separated electrodes and a capacitor dielectric that includes portions of different dielectric materials provided in a desired area ratio. The disclosure provided for selecting dielectrics and dielectric thicknesses, determining an area ratio that produces temperature and/or voltage independent MIM capacitors, and forming capacitive devices with the desired area ratio. In one embodiment, the capacitor dielectric includes at least one SiO dielectric portion and at least one SiN dielectric portion and a total capacitive area includes the SiN and SiO dielectric portions arranged such that the ratio of the area of the SiO portions to the area of the SiN portions is about 1.15:1.
摘要翻译：提供温度和/或电压无关的MIM电容器，以及用于制定用于半导体集成电路的MIM电容器的方法。垂直MIM电容结构包括至少两个垂直分离的电极和电容器电介质，其包括以期望的面积比提供的不同介电材料的部分。本公开提供用于选择电介质和介电厚度，确定产生温度和/或电压不依赖的MIM电容器的面积比，以及形成具有所需面积比的电容器件。在一个实施例中，电容器电介质包括至少一个SiO电介质部分和至少一个SiN电介质部分，并且总电容区域包括SiN和SiO电介质部分，其布置成使得SiO部分的面积与 SiN部分约为1.15:1。

69. 发明授权

US09064709B2 High breakdown voltage III-N depletion mode MOS capacitors 有权
标题翻译：高耐压III-N耗尽型MOS电容
公开(公告)号：US09064709B2
公开(公告)日：2015-06-23
申请号：US13631569
申请日：2012-09-28
申请人： Han Wui Then , Sansaptak Dasgupta , Gerhard Schrom , Valluri R. Rao , Robert S. Chau
发明人： Han Wui Then , Sansaptak Dasgupta , Gerhard Schrom , Valluri R. Rao , Robert S. Chau
IPC分类号： H01L27/06 , H01L29/93 , H01L29/66 , H01L29/94 , H01L27/08 , H01L29/06 , H01L29/205 , H01L29/04 , H01L29/20
CPC分类号： H01L27/0605 , H01L27/0805 , H01L29/045 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/66181 , H01L29/93 , H01L29/94
摘要： III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
摘要翻译：集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术。在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。

70. 发明授权

US09059133B2 Capacitor structure 有权
标题翻译：电容结构
公开(公告)号：US09059133B2
公开(公告)日：2015-06-16
申请号：US14467824
申请日：2014-08-25
申请人： Infineon Technologies AG
发明人： Andre Hanke , Oliver Nagy
IPC分类号： H01L29/00 , H01L49/02 , H01L23/48 , H01L27/08
CPC分类号： H01L28/40 , H01L23/481 , H01L27/0805 , H01L28/60 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： One or more embodiments relate to a semiconductor device, comprising: A semiconductor device, comprising: a semiconductor substrate; a plurality of first conductive vias, the first conductive vias electrically coupled together, each of the first conductive vias passing through the substrate; and a plurality of second conductive vias, the second conductive vias electrically coupled together, each of the second conductive vias passing through the substrate, the second conductive vias spacedly disposed from the first conductive vias, each of the second conductive vias laterally surrounding a respective one of the first conductive vias.
摘要翻译：一个或多个实施例涉及半导体器件，包括：半导体器件，包括：半导体衬底; 多个第一导电通孔，第一导电通孔电耦合在一起，每个第一导电通孔穿过基板; 以及多个第二导电通孔，所述第二导电通孔电耦合在一起，每个所述第二导电通孔穿过所述基板，所述第二导电通孔与所述第一导电通孔间隔开设置，所述第二导电通孔中的每一个横向地围绕相应的一个的第一导电通孔。

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