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61. 发明授权

US08896055B2 Accumulation type FinFET, circuits and fabrication method thereof 有权
标题翻译：积分型FinFET，电路及其制造方法
公开(公告)号：US08896055B2
公开(公告)日：2014-11-25
申请号：US13585436
申请日：2012-08-14
申请人： Chih Chieh Yeh , Chih-Sheng Chang , Clement Hsingjen Wann
发明人： Chih Chieh Yeh , Chih-Sheng Chang , Clement Hsingjen Wann
IPC分类号： H01L21/336 , H01L27/088 , H01L29/78 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/7851 , H01L21/823431 , H01L29/165 , H01L29/267 , H01L29/66795 , H01L29/7848 , H01L2029/7857
摘要： This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.
摘要翻译：本说明书涉及在基板上包括基板和翅片结构的鳍状场效应晶体管（FinFET）。鳍结构包括源极和漏极之间的沟道，其中源极，漏极和沟道具有第一类型掺杂物，并且沟道包括Ge，SiGe或III-V半导体中的至少一个。 FinFET还包括通道上的栅极介电层和栅极电介质层上的栅极。 FinFET还包括邻近栅极的衬底上的氮化物间隔物和氮化物间隔物和栅极之间以及氮化物间隔物和衬底之间的氧化物层。

62. 发明申请

US20140064006A1 JUNCTIONLESS SEMICONDUCTOR DEVICE HAVING BURIED GATE, APPARATUS INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：具有封盖的无连接半导体器件，包括其的装置以及制造半导体器件的方法
公开(公告)号：US20140064006A1
公开(公告)日：2014-03-06
申请号：US13722504
申请日：2012-12-20
申请人： SK HYNIX INC.
发明人： Kyung Kyu MIN , Min Soo YOO , Il Woong KWON
IPC分类号： H01L27/12 , G11C7/06 , G11C8/10 , H01L21/84
CPC分类号： H01L29/66484 , G11C7/06 , G11C8/10 , H01L21/265 , H01L21/845 , H01L27/1211 , H01L29/36 , H01L2029/7857
摘要： A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current.
摘要翻译：公开了一种具有掩埋栅极的无连接半导体器件，每个具有该掩埋栅极的模块和系统，以及用于形成半导体器件的方法。具有掩埋栅极的半导体器件的源极，漏极和主体掺杂有相同类型的杂质，使得无连接半导体器件不包括源极和主体之间或物体之间的PN结排水。结果，由GIDL引起的漏电流减小，使得半导体器件的工作特性得到改善，并且电流流动区域的尺寸增加，从而增加了工作电流。

63. 发明授权

US08476711B2 System for protection against electrostatic discharges in an electrical circuit 有权
标题翻译：用于防止电路中的静电放电的系统
公开(公告)号：US08476711B2
公开(公告)日：2013-07-02
申请号：US12176659
申请日：2008-07-21
申请人： Harald Gossner , Christian Russ
发明人： Harald Gossner , Christian Russ
IPC分类号： H01L27/06
CPC分类号： H01L27/1211 , H01L27/0288 , H01L29/42392 , H01L29/66795 , H01L29/785 , H01L29/8086 , H01L2029/7857
摘要： A gate controlled fin resistance element for use as an electrostatic discharge (ESD) protection element in an electrical circuit has a fin structure having a first connection region, a second connection region and a channel region formed between the first and second connection regions. Furthermore, the fin resistance element has a gate region formed at least over a part of the surface of the channel region. The gate region is electrically coupled to a gate control device, which gate control device controls an electrical potential applied to the gate region in such a way that the gate controlled fin resistance element has a high electrical resistance during a first operating state of the electrical circuit and a lower electrical resistance during a second operating state, which is characterized by the occurrence of an ESD event.
摘要翻译：在电路中用作静电放电（ESD）保护元件的栅极控制鳍电阻元件具有鳍状结构，其具有形成在第一和第二连接区域之间的第一连接区域，第二连接区域和沟道区域。此外，散热片电阻元件具有形成在通道区域的表面的至少一部分上的栅极区域。栅极区域电耦合到栅极控制装置，栅极控制装置控制施加到栅极区域的电位，使得栅极控制的鳍状电阻元件在电路的第一操作状态期间具有高电阻并且在第二操作状态期间具有较低的电阻，其特征在于发生ESD事件。

64. 发明申请

US20130099317A1 Fin-Based Adjustable Resistor 有权
标题翻译：散热片可调电阻
公开(公告)号：US20130099317A1
公开(公告)日：2013-04-25
申请号：US13277547
申请日：2011-10-20
申请人： Wei Xia , Xiangdong Chen
发明人： Wei Xia , Xiangdong Chen
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L2029/7857
摘要： According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel.
摘要翻译：根据一个示例性实施例，鳍状可调电阻器包括第一导电类型的鳍状沟道和围绕鳍状沟道的栅极。鳍状可调电阻器还包括第一导电类型的第一和第二端子，其与鳍状通道邻接并位于翅片通道的相对侧上。翅片通道相对于第一和第二端子较低掺杂。通过改变施加到栅极的电压来调节第一和第二端子之间的鳍状通道的电阻，从而实现基于鳍片的可调电阻器。门可以在鳍通道的至少两侧。在施加耗尽电压时，在鳍式通道中形成反转之前，可以耗尽鳍通道。

65. 发明授权

US08362567B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08362567B2
公开(公告)日：2013-01-29
申请号：US12309245
申请日：2007-07-12
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L21/70
CPC分类号： H01L29/045 , H01L21/02057 , H01L21/28194 , H01L21/28202 , H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/456 , H01L29/518 , H01L29/785 , H01L2029/7857
摘要： In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
摘要翻译：在半导体装置中，以峰 - 谷（PV）值为单位，平坦度为0.3nm以下的程度是通过在加有荧光的状态下加氢的超纯水冲洗硅表面而实现的通过在电极和硅之间设定0.2eV以下的功函数差来实现10-11＆OHgr·cm 2以下的接触电阻。因此，半导体器件可以在10GHz或更高的频率上工作。

66. 发明申请

US20120306002A1 ACCUMULATION TYPE FINFET, CIRCUITS AND FABRICATION METHOD THEREOF 有权
标题翻译：累积型FINFET，电路及其制造方法
公开(公告)号：US20120306002A1
公开(公告)日：2012-12-06
申请号：US13585436
申请日：2012-08-14
申请人： Chih Chieh YEH , Chih-Sheng CHANG , Clement Hsingjen WANN
发明人： Chih Chieh YEH , Chih-Sheng CHANG , Clement Hsingjen WANN
IPC分类号： H01L29/78 , H01L27/088 , H01L21/336
CPC分类号： H01L29/7851 , H01L21/823431 , H01L29/165 , H01L29/267 , H01L29/66795 , H01L29/7848 , H01L2029/7857
摘要： This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.
摘要翻译：本说明书涉及在基板上包括基板和翅片结构的鳍状场效应晶体管（FinFET）。鳍结构包括源极和漏极之间的沟道，其中源极，漏极和沟道具有第一类型掺杂物，并且沟道包括Ge，SiGe或III-V半导体中的至少一个。 FinFET还包括通道上的栅极介电层和栅极电介质层上的栅极。 FinFET还包括邻近栅极的衬底上的氮化物间隔物和氮化物间隔物和栅极之间以及氮化物间隔物和衬底之间的氧化物层。

67. 发明申请

US20120161202A1 JUNCTIONLESS ACCUMULATION-MODE DEVICES ON PROMINENT ARCHITECTURES, AND METHODS OF MAKING SAME 有权
标题翻译：无偿建筑物上的无连续累积模式设备及其制造方法
公开(公告)号：US20120161202A1
公开(公告)日：2012-06-28
申请号：US12978248
申请日：2010-12-23
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar P. Mudanai
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Titash Rakshit , Sivakumar P. Mudanai
IPC分类号： H01L29/772 , H01L21/28 , H01L21/336
CPC分类号： H01L29/775 , H01L29/0669 , H01L29/205 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L2029/7857
摘要： A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
摘要翻译：通过在JAM半导体主体的突出特征之下的反向偏压带将无连接累积模式（JAM）半导体器件从半导体衬底隔离。制造JAM器件的过程包括植入和外延。

68. 发明授权

US08203148B2 Semiconductor device and structure 有权
标题翻译：半导体器件及结构
公开(公告)号：US08203148B2
公开(公告)日：2012-06-19
申请号：US13173999
申请日：2011-06-30
申请人： Deepak C. Sekar , Zvi Or-Bach
发明人： Deepak C. Sekar , Zvi Or-Bach
IPC分类号： H01L29/10
CPC分类号： H01L27/2481 , H01L21/268 , H01L21/6835 , H01L21/76254 , H01L21/8221 , H01L21/84 , H01L21/845 , H01L27/0688 , H01L27/105 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L27/10897 , H01L27/11 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/11573 , H01L27/11578 , H01L27/1203 , H01L27/1211 , H01L27/228 , H01L27/2436 , H01L27/249 , H01L29/42392 , H01L29/7841 , H01L29/785 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L2029/7857 , H01L2221/6835
摘要： A device, comprising: a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline, wherein said first layer comprises first transistors, wherein said second layer comprises second transistors, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said first transistors and said second transistors are processed following the same lithography step.
摘要翻译：一种器件，包括：第一层和第二层，其中所述第一层和所述第二层都是单晶的，其中所述第一层包括第一晶体管，其中所述第二层包括第二晶体管，其中所述第二晶体管中的至少一个基本上覆盖所述第一晶体管中的一个，并且其中所述第一晶体管和所述第二晶体管都在相同的光刻步骤之后被处理。

69. 发明申请

US20100059830A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100059830A1
公开(公告)日：2010-03-11
申请号：US12309245
申请日：2007-07-12
申请人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
发明人： Tadahiro Ohmi , Akinobu Teramoto , Rihito Kuroda
IPC分类号： H01L29/417 , H01L27/092
CPC分类号： H01L29/045 , H01L21/02057 , H01L21/28194 , H01L21/28202 , H01L21/823807 , H01L21/823835 , H01L21/82385 , H01L21/84 , H01L27/1203 , H01L29/41766 , H01L29/456 , H01L29/518 , H01L29/785 , H01L2029/7857
摘要： In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
摘要翻译：在半导体装置中，以峰 - 谷（PV）值为单位，平坦度为0.3nm以下的程度是通过在加有荧光的状态下加氢的超纯水冲洗硅表面而实现的通过在电极和硅之间设定0.2eV以下的功函数差来实现10-11＆OHgr·cm 2以下的接触电阻。因此，半导体器件可以在10GHz或更高的频率上工作。

70. 发明申请

US20090278570A1 Circuit Configurations Having Four Terminal JFET Devices 有权
标题翻译：具有四个端子JFET器件的电路配置
公开(公告)号：US20090278570A1
公开(公告)日：2009-11-12
申请号：US12506848
申请日：2009-07-21
申请人： Ashok Kumar Kapoor
发明人： Ashok Kumar Kapoor
IPC分类号： H03K19/094
CPC分类号： H01L29/8086 , H01L29/785 , H01L2029/7857 , H01L2924/0002 , H03K19/09403 , H01L2924/00
摘要： Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.
摘要翻译：公开了使用四端接点场效应晶体管（JFET）的电路。这种电路可以包括各种静态和动态逻辑电路，触发器，多路复用器，三态驱动器，相位检测器，具有可变速度的逻辑，和/或具有以线性或非线性模式操作的这种四端JFET的模拟电路。

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