专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US09406357B2 Data capture system and method, and memory controllers and devices 有权
标题翻译：数据采集系统和方法，以及内存控制器和设备
公开(公告)号：US09406357B2
公开(公告)日：2016-08-02
申请号：US14148488
申请日：2014-01-06
申请人： Micron Technology, Inc.
发明人： Huy Vo
IPC分类号： G11C7/10 , G11C11/4093 , G11C11/406 , G11C11/408
CPC分类号： G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C11/406 , G11C11/4082 , G11C11/4093
摘要： Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system and method may generate a first set of periodic signals and a second set of periodic signals that differs from the first set. Either the first set of periodic signals or the second set of periodic signals may be selected and used to generate a set of data capture signals. The selection of either the first set or the second set may be made on the basis of the number of serial data digits in a previously captured burst of data. The data capture signals may then be used to capture a burst of serial data digits.
摘要翻译：数据采集系统和方法的实施例可以用在各种设备中，例如在存储器控制器和存储设备中。数据采集系统和方法可以产生与第一组不同的第一组周期信号和第二组周期性信号。可以选择第一组周期信号或第二组周期信号来生成一组数据捕获信号。可以基于先前捕获的数据突发中的串行数据数字的数量来进行第一组或第二组的选择。然后可以使用数据捕获信号来捕获串行数据数字的突发。

62. 发明申请

US20160218714A1 LEVEL SHIFTER CIRCUIT 审中-公开
标题翻译：水平更换电路
公开(公告)号：US20160218714A1
公开(公告)日：2016-07-28
申请号：US15088905
申请日：2016-04-01
申请人： Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
发明人： Jan SUNDERMEYER , Norbert WEBER
IPC分类号： H03K19/0185
CPC分类号： H03K19/018507 , G11C7/1084 , H03K5/003 , H03K19/00369
摘要： Embodiments of the present invention provide a level converter circuit with a resistor and a current adjustment circuit. The resistor is connected between an input and an output of the level converter circuit. The current adjustment circuit is configured to influence a current through the resistor such that an output voltage of the level converter circuit does not exceed a maximum allowable value.
摘要翻译：本发明的实施例提供一种具有电阻器和电流调节电路的电平转换器电路。电阻连接在电平转换器电路的输入和输出之间。电流调节电路被配置为影响通过电阻器的电流，使得电平转换器电路的输出电压不超过最大允许值。

63. 发明申请

US20160218699A1 APPARATUSES AND METHODS FOR VOLTAGE BUFFERING 有权
标题翻译：电压缓冲的装置和方法
公开(公告)号：US20160218699A1
公开(公告)日：2016-07-28
申请号：US14417105
申请日：2014-08-25
申请人： MIRCRON TECHNOLOGY, INC.
发明人： Wei Lu Chu
IPC分类号： H03K3/356 , G11C7/10 , G11C29/50
CPC分类号： H03K3/356 , G11C7/1084 , G11C29/50 , G11C2029/5004 , H03F3/347
摘要： An apparatuses and methods for buffering a voltage from a circuit without current drive ability are described. An example apparatus includes a voltage buffer that includes two identical stages. The first stage is configured to receive an input voltage and produce an intermediate voltage as an output. The second stage is configured to receive the intermediate voltage and provide an output voltage that is equal to the input voltage. The voltage buffer may be coupled to a current source. The second stage of the voltage buffer may have current drive ability.
摘要翻译：描述了用于缓冲来自电路的电压而不具有当前驱动能力的装置和方法。示例性装置包括包括两个相同级的电压缓冲器。第一级配置为接收输入电压并产生中间电压作为输出。第二级被配置为接收中间电压并提供等于输入电压的输出电压。电压缓冲器可以耦合到电流源。电压缓冲器的第二级可能具有电流驱动能力。

64. 发明申请

US20160197611A1 REFERENCE VOLTAGE TRAINING DEVICE AND METHOD THEREOF 有权
标题翻译：参考电压训练装置及其方法
公开(公告)号：US20160197611A1
公开(公告)日：2016-07-07
申请号：US14976716
申请日：2015-12-21
申请人： Samsung Electronics Co., Ltd.
发明人： Seok-Young KANG , Hun-Dae CHOI
IPC分类号： H03K19/0175 , G11C7/22
CPC分类号： H03K19/017509 , G11C5/147 , G11C7/062 , G11C7/1084 , G11C7/12 , G11C7/14 , G11C7/22 , G11C7/222 , G11C29/028 , G11C2207/2254
摘要： Provided are a reference voltage training device and a method thereof. The reference voltage training device includes a comparator configured to compare a toggle signal with a reference voltage and output a comparison signal, a duty cycle detector configured to check a duty ratio of the comparison signal, and a reference voltage level changing unit configured to fix the reference voltage when the duty ratio meets a predetermined condition and to change a level of the reference voltage when the duty ratio does not meet the predetermined condition. The comparator outputs a changed comparison signal using the changed reference voltage.
摘要翻译：提供了一种参考电压训练装置及其方法。参考电压训练装置包括：比较器，被配置为将触发信号与参考电压进行比较并输出比较信号;配置为检查比较信号的占空比的占空比检测器;以及参考电压电平改变单元，当占空比满足预定条件时的参考电压，并且当占空比不满足预定条件时改变参考电压的电平。比较器使用改变的参考电压输出改变的比较信号。

65. 发明授权

US09385721B1 Bulk driven low swing driver 有权
标题翻译：批量驱动低摆动驱动器
公开(公告)号：US09385721B1
公开(公告)日：2016-07-05
申请号：US14596772
申请日：2015-01-14
申请人： SanDisk Technologies Inc.
发明人： Srinivas Rajendra , Venkatesh Prasad Ramachandra
IPC分类号： G11C8/12 , H03K19/0185 , G11C16/06 , H03M1/34 , G11C8/10 , G11C7/10
CPC分类号： H03K19/018514 , G11C5/063 , G11C5/147 , G11C7/1006 , G11C7/1084 , G11C8/10 , G11C8/12 , G11C16/08
摘要： A circuit is presented to reduce power while transmitting high speed signals across a long length of wire on an integrated circuit. A PMOS is used as a low swing driver, where the PMOS is connected between the driver's output and ground. The gate of the PMOS is also set to ground, while the input signal is connected to the bulk. The output is then transmitted over the signal path to an analog receiver, where both single ended and differential embodiments are presented. For a single ended version, a reference voltage for the receiver can be provided by a second, similarly connected PMOS whose bulk has an input signal at an intermediate level of input swing at the transmitter PMOS.
摘要翻译：在集成电路上通过长度较长的导线传输高速信号时，呈现电路以降低功率。 PMOS用作低摆幅驱动器，其中PMOS连接在驱动器的输出和地之间。 PMOS的栅极也被设置为接地，而输入信号连接到本体。然后，输出通过信号路径传输到模拟接收机，其中呈现单端和差分实施例。对于单端版本，用于接收器的参考电压可以由第二个类似连接的PMOS提供，其大体上具有在发射器PMOS处的输入摆幅的中间电平处的输入信号。

66. 发明授权

US09383809B2 System and method for reducing memory I/O power via data masking 有权
标题翻译：通过数据屏蔽来减少存储器I / O功率的系统和方法
公开(公告)号：US09383809B2
公开(公告)日：2016-07-05
申请号：US14079620
申请日：2013-11-13
申请人： Qualcomm Incorporated
发明人： Dexter Chun , Haw-Jing Lo
IPC分类号： G06F1/00 , G06F1/32 , G11C7/10 , G11C11/4096 , G06F7/76
CPC分类号： G06F1/3275 , G06F1/32 , G06F1/3253 , G06F7/764 , G11C7/1006 , G11C7/1009 , G11C7/1057 , G11C7/1084 , G11C11/4096
摘要： Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.
摘要翻译：公开了用于降低存储器I / O功率的系统和方法。一个实施例是包括片上系统（SoC），DRAM存储器件和数据屏蔽功率降低模块的系统。 SoC包括一个内存控制器。 DRAM存储器件通过多个DQ引脚耦合到存储器控制器。数据屏蔽功率降低模块包括被配置为在数据屏蔽操作期间将DQ引脚驱动到功率节省状态的逻辑。

67. 发明申请

US20160163362A1 INPUT CIRCUIT OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME 有权
标题翻译：使用相同的半导体器件和半导体系统的输入电路
公开(公告)号：US20160163362A1
公开(公告)日：2016-06-09
申请号：US14634167
申请日：2015-02-27
申请人： SK hynix Inc.
发明人： Dae Suk KIM
IPC分类号： G11C7/10
CPC分类号： G11C7/22 , G11C5/04 , G11C7/1078 , G11C7/1084 , G11C29/1201 , H01L2224/16145 , H01L2924/15192 , H01L2924/15311 , H03K5/22
摘要： An input circuit of a semiconductor apparatus may include a first input buffer configured to receive a signal through a test input terminal and to output a first input signal, a second input buffer configured to receive a signal through a normal input terminal and to output a second input signal. The input circuit of the semiconductor apparatus may include a switching unit configured to transfer the signal inputted through the test input terminal to the second input buffer according to a test mode signal. The input circuit of the to semiconductor apparatus may include a comparison unit configured to compare the first input signal with the second input signal and to generate a comparison signal, and a storage unit configured to store the comparison signal.
摘要翻译：半导体装置的输入电路可以包括：第一输入缓冲器，被配置为通过测试输入端子接收信号并输出第一输入信号;第二输入缓冲器，被配置为通过正常输入端子接收信号，并输出第二输入缓冲器输入信号。半导体装置的输入电路可以包括：开关单元，被配置为根据测试模式信号将通过测试输入端子输入的信号传送到第二输入缓冲器。半导体装置的输入电路可以包括比较单元，其被配置为将第一输入信号与第二输入信号进行比较并产生比较信号;以及存储单元，被配置为存储比较信号。

68. 发明授权

US09361958B2 Semiconductor device and method for operating the same 有权
标题翻译：半导体装置及其操作方法
公开(公告)号：US09361958B2
公开(公告)日：2016-06-07
申请号：US14523528
申请日：2014-10-24
申请人： SK hynix Inc.
发明人： Choung-Ki Song
IPC分类号： G11C7/10 , G11C29/50 , G11C29/02 , G11C11/401
CPC分类号： G11C7/12 , G11C7/10 , G11C7/1048 , G11C7/1084 , G11C11/401 , G11C29/02 , G11C29/12 , G11C29/50 , G11C2207/105 , G11C2207/2254
摘要： A semiconductor device may include: a plurality of data pads; a plurality of data buffers each suitable for buffering a signal inputted through a first input node using a voltage inputted through a second input node, and outputting the buffered signal; and a calibration control unit suitable for generating a test signal in a calibration mode, adjusting the level of the test signal, receiving outputs of the plurality of data buffers while adjusting the level of the test signal, and adjusting offsets of the data buffers such that the logical values of the outputs of the data buffers transit when the test signal has a target level.
摘要翻译：半导体器件可以包括：多个数据焊盘; 多个数据缓冲器，每个数据缓冲器适于通过使用通过第二输入节点输入的电压缓冲通过第一输入节点输入的信号，并输出缓冲的信号; 以及校准控制单元，其适于在校准模式中生成测试信号，调整测试信号的电平，在调整测试信号的电平的同时接收多个数据缓冲器的输出，以及调整数据缓冲器的偏移量，使得当测试信号具有目标电平时，数据缓冲器的输出的逻辑值就会转移。

69. 发明授权

US09356577B2 Memory interface receivers having pulsed control of input signal attenuation networks 有权
标题翻译：具有脉冲控制输入信号衰减网络的存储器接口接收器
公开(公告)号：US09356577B2
公开(公告)日：2016-05-31
申请号：US14457508
申请日：2014-08-12
申请人： Hector Sanchez , Gayathri A. Bhagavatheeswaran
发明人： Hector Sanchez , Gayathri A. Bhagavatheeswaran
IPC分类号： H03L5/00 , H03H11/24 , G11C11/4093 , H03K5/08
CPC分类号： H03H11/24 , G11C7/1084 , G11C11/4093 , H03H7/24 , H03K5/084
摘要： Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.
摘要翻译：公开了用于存储器接口和相关方法的接收机，其具有输入信号衰减网络的脉冲控制。实施例包括DC共模衰减网络，AC耦合网络，脉冲发生器和放大器。脉冲发生器接收放大器的输出并产生部分地控制衰减网络的操作的脉冲信号。衰减网络产生具有降低的DC共模电平的衰减信号。该衰减信号与由AC耦合网络传递的AC分量组合。所得到的组合信号由放大器检测和放大。与放大器和脉冲发生器相比，不同的电压域用于衰减网络和AC耦合网络。通过在维持AC信号电平的同时衰减DC共模电平，所公开的实施例允许在宽范围的DC共模电平上进行适当的信号检测。

70. 发明申请

US20160125920A1 MEMORY DEVICE WITH LOW POWER OPERATION MODE 有权
标题翻译：具有低功耗操作模式的存储器件
公开(公告)号：US20160125920A1
公开(公告)日：2016-05-05
申请号：US14931291
申请日：2015-11-03
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： HYE-RAN KIM , TAE-YOUNG OH , SEONG-JIN JANG
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C5/147 , G11C5/148 , G11C7/1006 , G11C7/1045 , G11C7/1057 , G11C7/1084 , G11C8/12 , G11C2207/2227
摘要： A memory device that operates in a low-power operation mode includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the number of data items prefetched in the memory cell array according to a power mode during a read operation. The encoding and decoding changing circuit changes a level of data written in the memory cell array according to the power mode during a read operation.
摘要翻译：以低功率操作模式操作的存储器件包括存储单元阵列，页面大小改变电路以及编码和解码改变电路。页面大小改变电路在读取操作期间根据功率模式改变在存储单元阵列中预取的数据项的数量。编码和解码改变电路在读取操作期间根据功率模式改变写入存储单元阵列的数据的电平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式