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61. 发明授权

US08243491B2 Semiconductor integrated circuit including semiconductor memory 失效
标题翻译：半导体集成电路包括半导体存储器
公开(公告)号：US08243491B2
公开(公告)日：2012-08-14
申请号：US12884378
申请日：2010-09-17
申请人： Toshiki Hisada , Hiromitsu Mashita
发明人： Toshiki Hisada , Hiromitsu Mashita
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C7/18 , G11C2207/002 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit.
摘要翻译：根据一个实施例，存储单元阵列包括布置在位线和字线的交叉点处的存储单元。位线包括顺序排列的第一，第二，第三和第四位线。第一感测电路布置在存储单元阵列的第一端侧，电连接到第一和第三位线。第二感测电路布置在存储单元阵列的第二端侧上，电连接到第二和第四位线。第一连接区域布置在存储单元阵列和第一感测电路之间，并且包括连接到第一位线和第一感测电路的第一传输晶体管。第二连接区域布置在第一连接区域和第一感测电路之间，并且包括连接到第三位线和第一感测电路的第二传输晶体管。

62. 发明授权

US08238182B2 Semiconductor device and data processing system comprising semiconductor device 失效
公开(公告)号：US08238182B2
公开(公告)日：2012-08-07
申请号：US12881750
申请日：2010-09-14
申请人： Soichiro Yoshida , Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Soichiro Yoshida , Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/06
CPC分类号： G11C11/4096 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C11/4091 , G11C11/4097 , G11C2207/002
摘要： A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.

63. 发明授权

US08218386B2 Embedded memory databus architecture 失效
标题翻译：嵌入式内存数据总线架构
公开(公告)号：US08218386B2
公开(公告)日：2012-07-10
申请号：US12952560
申请日：2010-11-23
申请人： Richard C. Foss
发明人： Richard C. Foss
IPC分类号： G11C7/02
CPC分类号： G11C7/1069 , G11C7/06 , G11C7/1048 , G11C7/1051 , G11C11/4091 , G11C11/4093 , G11C11/4096 , G11C11/4097 , G11C2207/002 , G11C2207/005
摘要： A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge storage cells connected to the bitlines, each having an enable input connected to a wordline, the bit line sense amplifiers being connected in a two dimensional array, pairs of primary databuses being connected through first access transistors to plural corresponding bit line sense amplifiers in each row of the array, apparatus for enabling columns of the first access transistors, databus sense amplifiers each connected to a corresponding data bus pair, a secondary databus, the secondary databus being connected through second access transistors to the databus sense amplifiers, and apparatus for enabling the second access transistors, whereby each the primary databus pair may be shared by plural sense amplifiers in a corresponding row of the array and the secondary databus may be shared by plural primary databus pairs.
摘要翻译：具有位线对的动态随机存取存储器（DRAM），每对都连接到第一位线读出放大器，与形成阵列的位线对交叉的字线，连接到位线的电荷存储单元，每个具有连接到位线的使能输入字线，位线读出放大器以二维阵列连接，成对的初级数据总线通过第一存取晶体管连接到阵列的每一行中的多个相应的位线读出放大器，用于使第一存取晶体管的列，数据总线读出放大器各自连接到对应的数据总线对，辅助数据总线，次级数据总线通过第二存取晶体管连接到数据总线读出放大器，以及用于使能第二存取晶体管的装置，由此每个主数据总线对可以被多个阵列的相应行中的读出放大器和辅助数据总线可以由多个pri共享玛丽数据总线对。

64. 发明申请

US20120166753A1 CONFIGURABLE MEMORY BANKS OF A MEMORY DEVICE 审中-公开
标题翻译：存储设备的可配置存储器
公开(公告)号：US20120166753A1
公开(公告)日：2012-06-28
申请号：US13394533
申请日：2010-08-23
申请人： Thomas Vogelsang
发明人： Thomas Vogelsang
IPC分类号： G06F12/00
CPC分类号： G11C8/12 , G11C7/1012 , G11C7/1045 , G11C11/4087 , G11C11/4096 , G11C2207/002 , G11C2207/105
摘要： A memory device has a storage array having a plurality of accessible memory banks and a configurable first set of memory segments. The plurality of accessible memory banks include a second set of memory segments. During a first mode of operation, the first set of memory segments is configured to be an additional accessible memory bank. During a second mode of operation, a pair of memory segments in the first set of memory segments are configured to be an additional set of memory segments in each of the plurality of accessible memory banks.
摘要翻译：存储器件具有存储阵列，其具有多个可存取存储体和可配置的第一组存储器段。多个可存储存储体包括第二组存储器段。在第一操作模式期间，第一组存储器段被配置为附加的可访问存储体。在第二操作模式期间，第一组存储器段中的一对存储器段被配置为在多个可存取存储体的每一个中的另外一组存储器段。

65. 发明授权

US08199595B2 Techniques for sensing a semiconductor memory device 有权
标题翻译：用于感测半导体存储器件的技术
公开(公告)号：US08199595B2
公开(公告)日：2012-06-12
申请号：US12877044
申请日：2010-09-07
申请人： Philippe Bruno Bauser , Jean-Michel Daga
发明人： Philippe Bruno Bauser , Jean-Michel Daga
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/002 , G11C2207/005
摘要： Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.
摘要翻译：公开了用于感测半导体存储器件的技术。在一个特定示例性实施例中，这些技术可以被实现为包括包括多个存储器单元的存储单元阵列的装置。该装置还可以包括第一数据读出放大器电路，其包括具有通过位线耦合到多个存储单元中的至少一个的第一区域的放大器晶体管。该装置还可以包括数据读出放大器锁存电路，其包括经由放大器晶体管的第二区域耦合到数据读出放大器电路的第一输入节点。

66. 发明授权

US08179735B2 Using differential signals to read data on a single-end port 有权
标题翻译：使用差分信号读取单端口的数据
公开(公告)号：US08179735B2
公开(公告)日：2012-05-15
申请号：US12732931
申请日：2010-03-26
申请人： Jui-Jen Wu
发明人： Jui-Jen Wu
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C7/18 , G11C8/14 , G11C11/413 , G11C2207/002 , G11C2207/005
摘要： In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line.
摘要翻译：在与存储器单元中读取数据相关的一些实施例中，数据被驱动到驱动局部读出放大器的局部位线。根据存储器单元中的数据的逻辑电平以及局部位线，局部读出放大器将局部位线上的数据传送到全局位线。相邻全局位线用作全局读出放大器的参考，以读取全局位线和邻近全局位线上的差分数据。

67. 发明授权

US08174920B2 Semiconductor memory device and driving method of the same 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08174920B2
公开(公告)日：2012-05-08
申请号：US12711613
申请日：2010-02-24
申请人： Fumiyoshi Matsuoka , Takashi Ohsawa
发明人： Fumiyoshi Matsuoka , Takashi Ohsawa
IPC分类号： G11C7/02 , G11C11/24
CPC分类号： G11C11/4091 , G11C11/4076 , G11C2207/002 , G11C2207/005 , G11C2211/4016
摘要： A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch circuit latching data to the 1st and 2nd-SN; a first data line (DQ) from the 1st-SN to outside; and a 2nd-DQ from the 2nd-SN to outside, wherein write data is transmitted from the 1st and 2nd-DQ to the 1st and 2nd-SN corresponding to selected cells before the 1st and 2nd-TG are set to be a conductive state, when writing data into the selected cells to be written out of the cells, and write data in the 1st and 2nd-SN corresponding to the selected cells are started to be written into the selected cells, when the 1st and 2nd-TG are set to be a conductive state.
摘要翻译：存储器包括第一和第二位线（BL）; 第一和第二感测节点（SN）; 第一个BL和第一个SN之间的第一个传输门; 在第二BL和第二-SN之间的第二传输门（TG）; 锁存电路将数据锁存到第1和第2-SN; 第一个数据线（DQ）从第一个SN到外部; 以及从第2-SN到外部的第2-DQ，其中在将第1和第2 -TT设置为导通状态之前，将写入数据从第1和第2-DQ发送到对应于所选择的单元的第1和第2-SN 当将数据写入要被写入单元格的所选单元格中时，开始将与所选单元相对应的第1和第2-SN中的写入数据写入所选单元格，当设置第1和第2 -TG时成为导电状态。

68. 发明申请

US20120092940A1 Memory Device and Read Operation Method Thereof 有权
标题翻译：存储器件及其读取操作方法
公开(公告)号：US20120092940A1
公开(公告)日：2012-04-19
申请号：US12907263
申请日：2010-10-19
申请人： Chin-Hung Chang , Chia-Jung Chen , Su-Chueh Lo , Ken-Hui Chen , Kuen-Long Chang
发明人： Chin-Hung Chang , Chia-Jung Chen , Su-Chueh Lo , Ken-Hui Chen , Kuen-Long Chang
IPC分类号： G11C7/12 , G11C7/06
CPC分类号： G11C7/1048 , G11C7/06 , G11C7/08 , G11C7/106 , G11C7/12 , G11C7/18 , G11C2207/002
摘要： A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current.
摘要翻译：存储器件的读操作。响应于指示从不同页面读取数据的输入地址，所选择的字线，第一和第二全局位线和所选择的第一位线组被预充电。流过所选字线的第一单元电流，产生第一和所选择的第一位线组。产生流过第二全局位线组的第一参考电流。基于第一单元电流和第一参考电流来读取前半页数据。所选择的字线，第一和第二全局位线被保持预充电。产生流过所选字线的第二单元电流。产生第二个参考电流。基于第二单元电流和第二参考电流来读取第二半页数据。

69. 发明授权

US08154902B2 Bit line decoder architecture for NOR-type memory array 有权
标题翻译： NOR型存储器阵列的位线解码器架构
公开(公告)号：US08154902B2
公开(公告)日：2012-04-10
申请号：US13099792
申请日：2011-05-03
申请人： Pantas Sutardja
发明人： Pantas Sutardja
IPC分类号： G11C17/00 , G11C11/34 , G11C8/00
CPC分类号： G11C7/1048 , G11C16/0491 , G11C16/08 , G11C16/24 , G11C2207/002
摘要： An integrated circuit including a plurality of bit lines, a memory array, and a bit line decoder. The memory array includes a plurality of memory cells, wherein each memory cell is respectively coupled to (i) two corresponding bit lines of the plurality of bit lines. During sensing of a state of a given memory cell, the bit line decoder (i) precharges a first bit line of the two corresponding bit lines to which the given memory cell is coupled to a first voltage potential, including precharging all other bit lines on a same side of the memory array as the first bit line to the first voltage potential, and (ii) precharges a second bit line of the two corresponding bit lines to a second voltage potential, including precharging all other bit lines on a same side of the memory array as the second bit line to the second voltage potential.
摘要翻译：包括多个位线的集成电路，存储器阵列和位线解码器。存储器阵列包括多个存储器单元，其中每个存储器单元分别耦合到（i）多个位线中的两个对应的位线。在感测给定存储单元的状态期间，位线解码器（i）对给定存储单元耦合到的第一电压电位的两个对应位线的第一位线进行预充电，包括对所有其它位线进行预充电存储器阵列的与第一位线相同的一侧到第一电压电位，以及（ii）将两个相应位线的第二位线预充电到第二电压电位，包括对同一侧的所有其它位线进行预充电存储器阵列作为第二位线到第二电压电位。

70. 发明授权

US08130577B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08130577B2
公开(公告)日：2012-03-06
申请号：US12590417
申请日：2009-11-06
申请人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
发明人： Jong-Hak Won , Young-Soo An , Jung-Hyeon Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C5/025 , G11C7/1012 , G11C7/12 , G11C2207/002
摘要： A semiconductor memory device includes a sub memory cell array region having memory cells each connected between word lines extending in a first direction and bit lines extending in a second direction that is orthogonal to the first direction of extension of the word lines and a sub word line driver region disposed at a side of the sub memory cell array region in the first direction and including sub word line drivers that activate the word lines. A sensing region is disposed at a side of the sub memory cell array region in the second direction and including an equalizer that precharges the bit line in response to a signal transferred through a drive signal line and at least one first control signal driver that activates an inverted control signal line in response to a signal transferred through a control signal line. A conjunction region disposed at an intersection between the sub word line driver region and the sensing region, in which the inverted control signal line is connected to the drive signal line.
摘要翻译：半导体存储器件包括具有存储单元的子存储单元阵列区域，每个存储单元分别连接在沿第一方向延伸的字线和沿着与字线的第一延伸方向正交的第二方向延伸的位线和一个子字线驱动器区域，设置在副存储单元阵列区域的第一方向的一侧，并且包括激活字线的子字线驱动器。感测区域设置在副存储单元阵列区域的第二方向的一侧，并且包括响应于通过驱动信号线传送的信号而对位线进行预充电的均衡器，以及至少一个第一控制信号驱动器，其激活响应于通过控制信号线传送的信号的反相控制信号线。配置在副字线驱动器区域和感测区域之间的交叉点处的连接区域，其中反相控制信号线连接到驱动信号线。

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