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61. 发明授权

US09053963B2 Multiple well bias memory 有权
标题翻译：多个井偏置记忆
公开(公告)号：US09053963B2
公开(公告)日：2015-06-09
申请号：US13938314
申请日：2013-07-10
申请人： Samsung Electronics Co., Ltd.
发明人： Chung-ki Lee , Hong-sun Hwang , Hyung-shin Kwon , Jong-hyoung Lim
IPC分类号： G11C7/00 , H01L27/088 , G11C11/40 , G11C11/404 , G11C11/408 , H01L27/108 , G11C11/4094
CPC分类号： H01L27/088 , G11C11/40 , G11C11/404 , G11C11/4085 , G11C11/4094 , G11C2207/005 , H01L27/10897
摘要： A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively. The first voltage being lower than the second voltage.
摘要翻译：一种包括半导体衬底的多阱偏压存储器件; 第一导电类型的第一阱形成在半导体衬底中并具有形成在其中的存储单元; 以及形成在半导体衬底中的第一导电类型的第二阱，并且其中形成有用于感测和放大来自存储器单元的数据的读出放大器。第一和第二阱具有不同的掺杂浓度并分别偏置到第一和第二电压。第一电压低于第二电压。

62. 发明授权

US09029929B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US09029929B2
公开(公告)日：2015-05-12
申请号：US14263269
申请日：2014-04-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Toshihiko Saito
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/786 , H01L21/84 , H01L27/115 , H01L27/12 , H01L21/02 , G11C11/404
CPC分类号： H01L29/7869 , G11C11/404 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/84 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween. The capacitor is connected to the first transistor through one of the electrodes.
摘要翻译：其中的存储单元包括第一晶体管和电容器，并且存储对应于保持在电容器中的电位的数据。所述第一晶体管包括一对电极，与所述电极的侧面接触的绝缘膜，设置在所述电极之间的第一栅电极，所述绝缘膜设置在所述第一栅电极与每个电极之间，并且其顶表面处于下部比第一栅极电极上的第一栅极绝缘膜，与第一栅极绝缘膜和电极接触的氧化物半导体膜，至少在氧化物半导体膜上的第二栅极绝缘膜，和第二栅极电极在氧化物半导体膜上方，其间设置有第二栅极绝缘膜。电容器通过其中一个电极连接到第一晶体管。

63. 发明授权

US09025388B2 Method for kink compensation in a memory 有权
标题翻译：存储器中的扭结补偿方法
公开(公告)号：US09025388B2
公开(公告)日：2015-05-05
申请号：US14045492
申请日：2013-10-03
申请人： Micron Technology, Inc.
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04 , G11C16/10 , G11C11/56 , G11C16/34 , G11C11/404
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译：本公开涉及存储器扭结补偿。一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。在施加顺序递增的编程脉冲数之后施加接种电压。在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

64. 发明申请

US20150078066A1 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件的半导体存储器件和驱动方法
公开(公告)号：US20150078066A1
公开(公告)日：2015-03-19
申请号：US14552556
申请日：2014-11-25
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yasuhiko TAKEMURA
IPC分类号： G11C7/10 , G11C11/40 , G11C11/24
CPC分类号： G11C7/1078 , G11C7/1048 , G11C11/24 , G11C11/40 , G11C11/404 , G11C11/405 , G11C16/02
摘要： A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.
摘要翻译：提供功耗低的新型半导体存储器件。写入晶体管WTr_n_m的源极，读取晶体管RTr_n_m的栅极和电容器CS_n_m的一个电极彼此连接。写入晶体管WTr_n_m的栅极和漏极分别连接到写入字线WWL_n和写入位线WBL_m。电容器CS_n_m的另一个电极连接到读取字线RWL_n。读取晶体管RTr_n_m的漏极连接到读取位线RBL_m。这里，读出位线RBL_m的电位被输入到反相放大电路，例如触发器电路FF_m，由反相放大器电路反相。该反相电位被输出到写入位线WBL_m。

65. 发明授权

US08982608B2 Semiconductor device and data processing system 有权
标题翻译：半导体器件和数据处理系统
公开(公告)号：US08982608B2
公开(公告)日：2015-03-17
申请号：US13864329
申请日：2013-04-17
申请人： PS4 Luxco S.a.r.l.
发明人： Kazuhiko Kajigaya
IPC分类号： G11C11/24 , G11C8/12 , G11C11/404 , G11C11/4091
CPC分类号： G11C11/4094 , G11C8/12 , G11C11/24 , G11C11/404 , G11C11/4091 , G11C2211/4016
摘要： A semiconductor device having a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell, so that the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.
摘要翻译：一种半导体器件，具有包括电容器和具有浮体结构的选择晶体管的存储单元，连接到选择晶体管的位线，位线控制电路和放大从存储单元读出的信号的读出放大器。位线控制电路在存储单元的非访问周期期间将位线设置为第一电位，然后在存储单元的访问周期期间将位线设置为第二电位，使得数据保持时间可以通过减少存储器单元的数据存储节点处的泄漏电流来延长，使得可以减少用于数据保持的平均消耗电流。

66. 发明授权

US08953364B2 Voltage rail noise sensing circuit and method 有权
标题翻译：电压轨噪声检测电路及方法
公开(公告)号：US08953364B2
公开(公告)日：2015-02-10
申请号：US13622016
申请日：2012-09-18
申请人： Timothy M. Hollis
发明人： Timothy M. Hollis
IPC分类号： G11C11/24 , G11C11/404
CPC分类号： G11C11/404 , G11C7/02 , G11C11/40 , G11C11/4074 , G11C29/1201 , G11C29/48
摘要： Apparatus and methods level shift a direct current (DC) component of a voltage rail signal from a first DC level to a second DC level such that voltage rail noise can be determined. The actual voltage rail noise can be compared to an expected amount of noise for analysis and validation of simulation models. Such assessment can be used to validate simulation models used to refine a design of an integrated circuit or as part of built-in self test.
摘要翻译：装置和方法将电压轨信号的直流（DC）分量从第一直流电平转换到第二直流电平，从而可以确定电压轨道噪声。实际的电压轨噪声可以与预期的噪声量进行比较，以便分析和验证仿真模型。这种评估可用于验证用于改进集成电路设计的模拟模型，或作为内置自检的一部分。

67. 发明申请

US20140369111A1 Semiconductor Memory Device And Method For Driving The Same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20140369111A1
公开(公告)日：2014-12-18
申请号：US14474396
申请日：2014-09-02
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yasuhiko Takemura
IPC分类号： G11C11/404 , G11C11/408 , G11C11/4094 , H01L27/108
CPC分类号： H01L27/10897 , G11C7/02 , G11C8/14 , G11C11/404 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10805 , H01L27/10811 , H01L27/10873 , H01L27/10894 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255
摘要： In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m—1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
摘要翻译：在常规DRAM中，当电容器的电容减小时，容易发生读取数据的错误。多个单元被连接到一个位线MBL_m。每个单元包括子位线SBL_n_m和4到64个存储单元（存储单元CL_n_m-1等）。此外，每个单元包括选择晶体管STr1_n_m和STr2_n_m，作为互补反相器等的放大器电路AMP_n_m连接到选择晶体管STr2_n_m。由于子位线SBL_n_m的寄生电容足够小，所以每个存储单元的电容器中的电荷引起的电位变化都可以被放大器电路AMP_n_m放大而没有错误，并且可以被输出到位线。

68. 发明授权

US08837202B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08837202B2
公开(公告)日：2014-09-16
申请号：US13236965
申请日：2011-09-20
申请人： Yasuhiko Takemura
发明人： Yasuhiko Takemura
IPC分类号： G11C11/24
CPC分类号： H01L27/10897 , G11C7/02 , G11C8/14 , G11C11/404 , G11C11/4076 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10805 , H01L27/10811 , H01L27/10873 , H01L27/10894 , H01L27/1207 , H01L27/1225 , H01L27/124 , H01L27/1255
摘要： In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m—1 or the like). Further, each cell includes selection transistors STr1—n—m and STr2—n—m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2—n—m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
摘要翻译：在常规DRAM中，当电容器的电容减小时，容易发生读取数据的错误。多个单元被连接到一个位线MBL_m。每个单元包括子位线SBL_n_m和4至64个存储单元（存储单元CL_n_m-1等）。此外，每个单元包括选择晶体管STr1-n-m和STr2-n-m，作为互补反相器等的放大器电路AMP_n_m连接到选择晶体管STr2-n-m。由于子位线SBL_n_m的寄生电容足够小，所以每个存储单元的电容器中的电荷引起的电位变化都可以被放大器电路AMP_n_m放大而没有错误，并且可以被输出到位线。

69. 发明申请

US20140204657A1 SRAM VOLTAGE ASSIST 有权
标题翻译： SRAM电压辅助
公开(公告)号：US20140204657A1
公开(公告)日：2014-07-24
申请号：US13748499
申请日：2013-01-23
申请人： NVIDIA CORPORATION
发明人： William James Dally
IPC分类号： G11C11/412
CPC分类号： G11C11/4125 , G11C11/404 , G11C11/419
摘要： The disclosure provides for an SRAM array having a plurality of wordlines and a plurality of bitlines, referred to generally as SRAM lines. The array has a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines. The SRAM array further includes voltage boost circuitry operatively coupled with the cells, the voltage boost circuitry being configured to provide an amount of voltage boost that is based on an address of a cell to be accessed and/or to provide this voltage boost on an SRAM line via capacitive charge coupling.
摘要翻译：本公开提供了具有多个字线和多个位线的SRAM阵列，通常称为SRAM线。该阵列具有多个单元，每个单元由字线之一和位线之一的交点定义。所述SRAM阵列还包括与所述单元操作地耦合的升压电路，所述升压电路被配置为提供基于待访问的单元的地址和/或在SRAM上提供该电压升压的一定量的升压电压线通过电容电荷耦合。

70. 发明授权

US08787072B2 Floating-body/gate DRAM cell 失效
标题翻译：浮体/门DRAM单元
公开(公告)号：US08787072B2
公开(公告)日：2014-07-22
申请号：US13124066
申请日：2009-12-29
申请人： Jerry G. Fossum , Zhichao Lu
发明人： Jerry G. Fossum , Zhichao Lu
IPC分类号： G11C11/00 , G11C11/36 , H01L27/12
CPC分类号： H01L27/10802 , G11C11/404 , G11C2211/4016 , H01L27/108 , H01L29/7391 , H01L29/7841
摘要： Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.
摘要翻译：提供存储单元结构和偏置方案。某些实施例涉及改进的浮体门电池，其可以提供改进的保持时间。在一个实施例中，栅极二极管用于驱动电池的第二晶体管结构的栅极。在另一实施例中，使用体耦源（BTS）场效应晶体管来驱动单元的第二晶体管结构的栅极。

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