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61. 发明申请

US20170097824A1 CHAINED SPLIT EXECUTION OF FUSED COMPOUND ARITHMETIC OPERATIONS 审中-公开
公开(公告)号：US20170097824A1
公开(公告)日：2017-04-06
申请号：US15202351
申请日：2016-07-05
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： THOMAS ELMER , NIKHIL A. PATIL
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/3836 , G06F9/3893
摘要： A microprocessor is configured for unchained and chained modes of split execution of a fused compound arithmetic operation. In both modes of split execution, a first execution unit executes only a first part of the fused compound arithmetic operation and produces an intermediate result thereof, and a second instruction execution unit receives the intermediate result and executes a second part of the fused compound arithmetic operation to produce a final result. In the unchained mode, execution is accomplished by dispatching separate split-execution microinstructions to the first and second instruction execution units. In the chained mode, execution is accomplished by dispatching a single split-execution microinstruction to the first instruction execution unit and sending a chaining control signal or signal group to the second execution unit, causing it to execute its part of the fused arithmetic operation without needing an instruction.

62. 发明授权

US09501286B2 Microprocessor with ALU integrated into load unit 有权
标题翻译：具有ALU的微处理器集成到负载单元中
公开(公告)号：US09501286B2
公开(公告)日：2016-11-22
申请号：US12609169
申请日：2009-10-30
申请人： Gerard M. Col , Colin Eddy , Rodney E. Hooker
发明人： Gerard M. Col , Colin Eddy , Rodney E. Hooker
IPC分类号： G06F9/38 , G06F9/30 , G06F12/08
CPC分类号： G06F9/3875 , G06F9/3001 , G06F9/3004 , G06F9/30043 , G06F9/30145 , G06F9/3017 , G06F9/3893 , G06F12/0875
摘要： A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored. The load unit reads the source operand from the cache memory. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The load unit outputs the result for subsequent retirement to the destination register.
摘要翻译：超标量流水线微处理器包括由其指令集架构定义的寄存器组，高速缓冲存储器，执行单元和负载单元，耦合到高速缓冲存储器并且与其他执行单元不同。负载单元包括一个ALU。加载单元接收指定源操作数的存储器地址的指令，要在源操作数上执行的用于生成结果的操作以及要存储结果的寄存器集的目标寄存器。加载单元从缓存中读取源操作数。 ALU对源操作数执行操作以生成结果，而不是将源操作数转发到微处理器的任何其他执行单元，以对源操作数执行操作以生成结果。加载单元将结果退出到目的地寄存器。

63. 发明授权

US09384168B2 Vector matrix product accelerator for microprocessor integration 有权
标题翻译：用于微处理器集成的矢量矩阵乘积加速器
公开(公告)号：US09384168B2
公开(公告)日：2016-07-05
申请号：US13914731
申请日：2013-06-11
申请人： Analog Devices Global
发明人： Mikael Mortensen
IPC分类号： G06F17/16 , G06F9/30 , G06F9/38
CPC分类号： G06F17/16 , G06F9/3001 , G06F9/30036 , G06F9/3824 , G06F9/3893
摘要： In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port.
摘要翻译：在至少一个示例性实施例中，提供了微处理器电路，其包括经由包括预定整数数据线（J）的数据存储器总线耦合到数据存储器的微处理器核心; 单端口数据存储器，其被配置为以预定向量元素顺序存储N个元素向量的向量输入元素，并存储包括M列矩阵输入元素和N行矩阵输入元素的M×N矩阵的矩阵输入元素 ; 矢量矩阵乘积加速器，其包括被配置为将所述N个元素向量和所述矩阵相乘以计算M元素结果向量的数据路径，所述向量矩阵乘积加速器包括：将所述数据存储器总线连接到所述向量矩阵乘积加速器的输入/输出端口; 多个向量输入寄存器，用于存储通过输入/输出端口接收的各个输入向量元素。

64. 发明授权

US09270460B2 Instructions to perform JH cryptographic hashing in a 256 bit data path 有权
标题翻译：在256位数据路径中执行JH加密散列的指令
公开(公告)号：US09270460B2
公开(公告)日：2016-02-23
申请号：US13995457
申请日：2011-12-22
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F21/00 , H04L9/14 , H04L9/32 , G06F9/30 , G06F9/38 , G06F21/60
CPC分类号： H04L9/14 , G06F9/30007 , G06F9/30032 , G06F9/30036 , G06F9/3893 , G06F21/602 , H04L9/3239
摘要： A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
摘要翻译：描述了一种方法。该方法包括执行一个或多个JH_SBOX_L指令以在JH状态上执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换。

65. 发明授权

US09235414B2 SIMD integer multiply-accumulate instruction for multi-precision arithmetic 有权
标题翻译：用于多精度算术的SIMD整数乘法累加指令
公开(公告)号：US09235414B2
公开(公告)日：2016-01-12
申请号：US13992728
申请日：2011-12-19
申请人： Vinodh Gopal , Gilbert M. Wolrich , Erdinc Ozturk , James D. Guilford , Kirk S. Yap , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Erdinc Ozturk , James D. Guilford , Kirk S. Yap , Sean M. Gulley , Wajdi K. Feghali , Martin G. Dixon
IPC分类号： G06F7/52 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30036 , G06F9/30101 , G06F9/3893
摘要： A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.
摘要翻译：乘法和累加（MAC）指令允许有效执行无符号整数乘法。 MAC指令表示作为第一操作数的第一向量寄存器，作为第二操作数的第二向量寄存器和作为目的地的第三向量寄存器。第一向量寄存器存储第一因子，第二向量寄存器存储部分和。执行MAC指令以将第一因子与隐含的第二因子相乘以生成乘积，并将部分和添加到乘积以生成结果。第一个因素，隐含的第二个因子和部分和具有相同的数据宽度，产品的数据宽度是两倍。结果的最大一半存储在第三向量寄存器中，结果的最低有效半存储在第二向量寄存器中。

66. 发明申请

US20160004509A1 CALCULATION CONTROL INDICATOR CACHE 有权
标题翻译：计算控制指示器缓存
公开(公告)号：US20160004509A1
公开(公告)日：2016-01-07
申请号：US14748956
申请日：2015-06-24
申请人： VIA ALLIANCE SEMICONDUCTOR CO, LTD.
发明人： THOMAS ELMER
IPC分类号： G06F7/487 , G06F7/485 , G06F17/16
CPC分类号： G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/3017 , G06F9/30185 , G06F9/38 , G06F9/3893 , G06F17/16
摘要： An arithmetic operation is performed using a first instruction execution unit to generate an intermediate result vector and a plurality of calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The intermediate result vector and the plurality of calculation control indicators are stored in memory external to the instruction execution unit, and later read by a second instruction execution unit to complete the arithmetic operation.
摘要翻译：使用第一指令执行单元执行算术运算，以产生中间结果向量和指示如何继续从中间结果向量生成最终结果的后续计算的多个计算控制指示符。中间结果矢量和多个计算控制指示器存储在指令执行单元外部的存储器中，并且稍后由第二指令执行单元读取以完成算术运算。

67. 发明申请

US20160004506A1 STANDARD FORMAT INTERMEDIATE RESULT 有权
标题翻译：标准格式中间结果
公开(公告)号：US20160004506A1
公开(公告)日：2016-01-07
申请号：US14749002
申请日：2015-06-24
申请人： VIA ALLIANCE SEMICONDUCTOR CO, LTD.
发明人： THOMAS ELMER
IPC分类号： G06F7/483 , G06F9/30 , G06F9/38 , G06F7/544
CPC分类号： G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/3017 , G06F9/30185 , G06F9/38 , G06F9/3893 , G06F17/16
摘要： A microprocessor comprises an instruction pipeline, a shared memory, and first and second arithmetic processing units in the instruction pipeline, each capable of reading or receiving operands from and writing or providing results to the shared memory. The first arithmetic processing unit performs a first portion of a mathematical operation to produce an intermediate result vector that is not a complete, final result of the mathematical operation. The first arithmetic processing unit generates a plurality of non-architectural calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The second arithmetic processing unit performs a second portion of the mathematical operation, in accordance with the calculation control indicators, to produce a complete, final result of the mathematical operation.
摘要翻译：微处理器包括指令流水线，共享存储器以及指令流水线中的第一和第二算术处理单元，每个能够读取或接收来自共享存储器的操作数和向其写入或提供结果。第一算术处理单元执行数学运算的第一部分以产生不是数学运算的完整最终结果的中间结果矢量。第一算术处理单元生成多个非架构计算控制指示符，其指示如何继续从中间结果向量生成最终结果的后续计算。第二算术处理单元根据计算控制指示符执行数学运算的第二部分，以产生数学运算的完整的最终结果。

68. 发明申请

US20150212972A1 DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING SCAN OPERATIONS 有权
标题翻译：数据处理设备和执行扫描操作的方法
公开(公告)号：US20150212972A1
公开(公告)日：2015-07-30
申请号：US14165967
申请日：2014-01-28
申请人： ARM LIMITED
发明人： Matthias Lothar BOETTCHER , Mbou EYOLE-MONONO , Giacomo GABRIELLI
IPC分类号： G06F15/78 , G06F9/30
CPC分类号： G06F15/78 , G06F9/3001 , G06F9/30036 , G06F9/30098 , G06F9/3017 , G06F9/3875 , G06F9/3887 , G06F9/3893
摘要： A data processing apparatus and method are provided for executing a vector scan instruction. The data processing apparatus comprises a vector register store configured to store vector operands, and processing circuitry configured to perform operations on vector operands retrieved from said vector register store. Further, control circuitry is configured to control the processing circuitry to perform the operations required by one or more instructions, said one or more instructions including a vector scan instruction specifying a vector operand comprising N vector elements and defining a scan operation to be performed on a sequence of vector elements within the vector operand. The control circuitry is responsive to the vector scan instruction to partition the N vector elements of the specified vector operand into P groups of adjacent vector elements, where P is between 2 and N/2, and to control the processing circuitry to perform a partitioned scan operation yielding the same result as the defined scan operation. The processing circuitry is configured to perform the partitioned scan operation by performing separate scan operations on those vector elements of the sequence contained within each group to produce intermediate results for each group, and to perform a computation operation to combine the intermediate results into a final result vector operand containing a sequence of result vector elements. The partitioned scan operation approach of the present invention enables a balance to be achieved between energy consumption and performance.
摘要翻译：提供了一种用于执行向量扫描指令的数据处理装置和方法。数据处理装置包括被配置为存储向量操作数的向量寄存器存储器，以及被配置为对从所述向量寄存器存储器检索的向量操作数执行操作的处理电路。此外，控制电路被配置为控制处理电路执行一个或多个指令所需的操作，所述一个或多个指令包括指定包括N个向量元素的向量操作数的向量扫描指令，并且定义要在向量操作数中向量元素的序列。控制电路响应于矢量扫描指令将指定矢量操作数的N个向量元素划分为相邻矢量元素的P组，其中P在2和N / 2之间，并且控制处理电路执行分区扫描操作产生与定义的扫描操作相同的结果。处理电路被配置为通过对包含在每个组中的序列的那些矢量元素执行单独的扫描操作来执行分割扫描操作，以产生每个组的中间结果，并且执行计算操作以将中间结果组合成最终结果向量操作数包含一系列结果向量元素。本发明的划分扫描操作方法能够在能量消耗和性能之间实现平衡。

69. 发明申请

US20150089197A1 METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION 审中-公开
公开(公告)号：US20150089197A1
公开(公告)日：2015-03-26
申请号：US14557372
申请日：2014-12-01
申请人： Intel Cororation
发明人： Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/3816 , G06F9/3893
摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

70. 发明申请

US20150089196A1 METHOD AND APPARATUS FOR PERFORMING A SHIFT AND EXCLUSIVE OR OPERATION IN A SINGLE INSTRUCTION 审中-公开
公开(公告)号：US20150089196A1
公开(公告)日：2015-03-26
申请号：US14557360
申请日：2014-12-01
申请人： Intel Cororation
发明人： Vinodh Gopal , James D. Guilford , Erdinc Ozturk , Wajdi K. Feghali , Gilbert M. Wolrich , Martin G. Dixon
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/3816 , G06F9/3893
摘要： Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

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