专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20160006786A1 Domain-Specific Hardwired Web Server Machine 有权
标题翻译：域特定的硬连线Web服务器机器
公开(公告)号：US20160006786A1
公开(公告)日：2016-01-07
申请号：US14321097
申请日：2014-07-01
申请人： Hackproof Technologies, Inc.
发明人： Joseph Mitola, III
IPC分类号： H04L29/08
CPC分类号： G06Q20/405 , G06F9/524 , G06F11/00 , G06F11/0721 , G06F11/0793 , G06F21/56 , G06F21/57 , G06F21/71 , G06F21/76 , G06N99/005 , H04L47/70 , H04L63/123 , H04L67/02 , Y02D30/40
摘要： A domain-specific hardwired symbolic web server machine is described that processes information via the hardwired mapping of symbols from one or more domains onto other such domains, computing and communicating with improved security and reduced power consumption because it has no CPU, no Random Access Memory (RAM), no instruction registers, no Instruction Set Architecture (ISA), no operating system (OS) and no applications programming. The machine provides web services by recognizing legal requests such as HTTP GET request and responding with an HTML web page. In some embodiments, the machine has no unconstrained RAM into which malware may insert itself and needs no anti-virus software.
摘要翻译：描述了一种特定于域的硬连线符号Web服务器机器，其通过经由来自一个或多个域的符号的硬连线映射来处理信息到其他这样的域上，由于没有CPU而没有CPU，无任何随机存取存储器（RAM），无指令寄存器，无指令集架构（ISA），无操作系统（OS），无应用程序编程。该机器通过识别诸如HTTP GET请求之类的法律请求和使用HTML网页进行响应来提供Web服务。在一些实施例中，机器没有无约束的RAM，恶意软件可能插入其中，并且不需要防病毒软件。

62. 发明授权

US09230091B2 Managing use of a field programmable gate array with isolated components 有权
标题翻译：管理使用具有隔离组件的现场可编程门阵列
公开(公告)号：US09230091B2
公开(公告)日：2016-01-05
申请号：US13528400
申请日：2012-06-20
申请人： Brian A. LaMacchia , Edmund B. Nightingale , Paul Barham
发明人： Brian A. LaMacchia , Edmund B. Nightingale , Paul Barham
IPC分类号： G06F21/76 , G06F21/44 , G06F21/85
CPC分类号： G06F21/445 , G06F21/76 , G06F21/85
摘要： Field programmable gate arrays can be used as a shared programmable co-processor resource in a general purpose computing system. Components of an FPGA are isolated to protect the FPGA and data transferred between the FPGA and other components of the computer system. For example, data written by the FPGA to memory is encrypted, and is decrypted within the FPGA when read back from memory. Data transferred between the FPGA and other components such as the CPU or GPU, whether directly or through memory, can similarly be encrypted using cryptographic keys known to the communicating components. Transferred data also can be digitally signed by the FPGA or other component to provide authentication. Code for programming the FPGA can be encrypted and signed by the author, loaded into the FPGA in an encrypted state, and then decrypted and authenticated by the FPGA itself, before programming the FPGA with the code.
摘要翻译：现场可编程门阵列可用作通用计算系统中的共享可编程协处理器资源。 FPGA的组件是隔离的，用于保护FPGA和FPGA与计算机系统其他组件之间传输的数据。例如，由FPGA写入存储器的数据被加密，并在从存储器读回时在FPGA内进行解密。 FPGA和GPU等其他组件（无论是直接还是通过内存）之间传输的数据可以使用通信组件已知的加密密钥进行加密。传输的数据也可以由FPGA或其他组件进行数字签名，以提供认证。编程FPGA的代码可以由作者进行加密和签名，在加密状态下加载到FPGA中，然后在使用代码编程FPGA之前，由FPGA自身对其进行解密和认证。

63. 发明授权

US09218506B2 Methods and systems for preventing hardware trojan insertion 有权
标题翻译：防止硬件木马插入的方法和系统
公开(公告)号：US09218506B2
公开(公告)日：2015-12-22
申请号：US14204656
申请日：2014-03-11
申请人： University of Connecticut
发明人： Mohammad Tehranipoor , Kan Xiao
IPC分类号： G06F21/76 , G06F21/75 , G06F21/70 , G06F21/71
CPC分类号： G06F21/76 , G06F21/70 , G06F21/71 , G06F21/75
摘要： Provided are methods and systems for preventing hardware Trojan insertion. An example method can comprise determining unused space in an integrated circuit (IC), selecting a plurality of built-in self-authentication (BISA) filler cells based on the determined unused space, and placing the selected plurality of BISA filler cells onto the unused space. The plurality of BISA filler cells can be connected to form a plurality of BISA blocks. The plurality of BISA blocks can correspond to a plurality of signatures. A modification of one or more BISA filler cell can lead to an alteration of one or more signatures.
摘要翻译：提供了防止硬件木马插入的方法和系统。示例性方法可以包括确定集成电路（IC）中的未使用空间，基于所确定的未使用空间来选择多个内置自认证（BISA）填充单元，以及将所选择的多个BISA填充单元放置在未使用的空间空间。可以连接多个BISA填充单元以形成多个BISA块。多个BISA块可以对应于多个签名。一个或多个BISA填充单元的修改可导致一个或多个签名的改变。

64. 发明申请

US20150347760A1 PERTURBATION OF FIELD PROGRAMMABLE GATE ARRAY CODE TO PREVENT SIDE CHANNEL ATTACK 有权
标题翻译：现场可编程门阵列代码防止侧向通道攻击
公开(公告)号：US20150347760A1
公开(公告)日：2015-12-03
申请号：US14295286
申请日：2014-06-03
申请人： Empire Technology Development LLC
发明人： Ezekiel Kruglick
IPC分类号： G06F21/57
CPC分类号： G06F21/577 , G06F21/50 , G06F21/556 , G06F21/57 , G06F21/572 , G06F21/70 , G06F21/75 , G06F21/76 , G06F2221/033 , G06F2221/034
摘要： Technologies are provided to automatically vary a structure of a netlist computation arranged to configure a field programmable gate array (FPGA). In an example scenario, an FPGA netlist may be received from a client to configure the FPGA. A perturbation generator may be activated in response to a detection of one or more security risk factors associated with the netlist. The netlist may be altered through schemes designed to repair one or more FPGAs. The repair schemes may be used to repair the FPGAs to work around failed cells and failed sub-cells. The perturbation generator may produce a false map of failed cells. The false map may be used to generate different timings and different intermediate values associated with the netlist to generate an alternate netlist. The alternate netlist may be used to configure the FPGA to prevent side channel attacks.
摘要翻译：提供了技术来自动地改变布置成配置现场可编程门阵列（FPGA）的网表计算的结构。在一个示例场景中，可以从客户端接收FPGA网络表以配置FPGA。扰动发生器可以响应于检测到与网表相关联的一个或多个安全风险因素而被激活。可以通过设计用于修复一个或多个FPGA的方案来改变网表。修复方案可用于修复FPGA以解决故障单元和故障子单元。扰动发生器可能会产生故障单元的虚拟映射。假映射可用于生成与网表相关联的不同定时和不同中间值，以生成备用网表。备用网表可用于配置FPGA以防止侧信道攻击。

65. 发明申请

US20150280907A1 DEVICE WITH RESISTANCE TO DIFFERENTIAL POWER ANALYSIS AND OTHER EXTERNAL MONITORING ATTACKS 有权
标题翻译：具有抵抗差分功率分析和其他外部监测攻击的装置
公开(公告)号：US20150280907A1
公开(公告)日：2015-10-01
申请号：US14737154
申请日：2015-06-11
申请人： Cryptography Research, Inc.
发明人： Paul C. Kocher , Pankaj Rohatgi , Joshua M. Jaffe
IPC分类号： H04L9/00 , H04L9/16 , H04L9/06
CPC分类号： G06F21/575 , G06F8/71 , G06F9/44505 , G06F12/1408 , G06F21/556 , G06F21/602 , G06F21/755 , G06F21/76 , G06F2212/402 , G06F2221/034 , G06F2221/2107 , G06F2221/2125 , G06F2221/2145 , H04L9/003 , H04L9/0631 , H04L9/085 , H04L9/0861 , H04L9/088 , H04L9/0894 , H04L9/16 , H04L9/3236 , H04L9/3247 , H04L63/0428 , H04L63/0869 , H04L2209/24 , H04L2209/38 , H04L2209/56 , H04L2463/061
摘要： A device includes storage hardware to store a secret value and processing hardware coupled to the storage hardware. The processing hardware is to receive an encrypted data segment with a validator and derive a decryption key using the secret value and a plurality of entropy distribution operations. The processing hardware is further to verify, using the received validator, that the encrypted data segment has not been modified. The processing hardware is further to decrypt the encrypted data segment using the decryption key to produce a decrypted data segment responsive to verifying that the encrypted data segment has not been modified.
摘要翻译：设备包括存储硬件以存储与存储硬件耦合的秘密值和处理硬件。处理硬件是使用验证器接收加密数据段，并使用秘密值和多个熵分布操作导出解密密钥。处理硬件还使用接收到的验证器验证加密的数据段未被修改。所述处理硬件还用于使用所述解密密钥对所述加密数据段进行解密，以响应于验证所述加密数据段未被修改而产生解密的数据段。

66. 发明授权

US09147074B2 Method and apparatus for securing CPUS booted using attached flash memory devices 有权
标题翻译：使用连接的闪存设备启动CPUS的方法和设备
公开(公告)号：US09147074B2
公开(公告)日：2015-09-29
申请号：US13114831
申请日：2011-05-24
申请人： Anthony H. Grieco , Chirag K. Shroff , Robert T. Bell
发明人： Anthony H. Grieco , Chirag K. Shroff , Robert T. Bell
IPC分类号： G06F9/00 , G06F15/177 , G06F21/57 , G06F9/44
CPC分类号： G06F21/575 , G06F9/4401 , G06F9/4416 , G06F21/76
摘要： The present disclosure describes techniques evaluating compute and/or thermal loads (among other things) to aid in managing a collection of one or more containerized or modular data centers. For example, forecasts (or real-time measurements) of environmental factors (as well as projected computing demands) may be used to tailor the compute loads, cooling strategies or other metric of data center operations for a network of containerized or modular data centers. Doing so allows an operator of such a data center network to manage specific operational goals in real time.
摘要翻译：本公开描述了评估计算和/或热负载（除其他之外）以帮助管理一个或多个集装箱或模块化数据中心的集合的技术。例如，可以使用环境因素的预测（或实时测量）（以及预计的计算需求）来定制集装箱或模块化数据中心网络的计算负载，冷却策略或数据中心操作的其他度量。这样做允许这样的数据中心网络的运营商实时管理特定的操作目标。

67. 发明申请

US20150220744A1 SYSTEM FOR EXECUTION OF SECURITY RELATED FUNCTIONS 有权
标题翻译：执行安全相关职能的制度
公开(公告)号：US20150220744A1
公开(公告)日：2015-08-06
申请号：US14176773
申请日：2014-02-10
申请人： LSI CORPORATION
发明人： Krishnan Srinivasan , Igor Kucherenko , Nikola Radovanovic
IPC分类号： G06F21/60 , H04L9/30 , H04L9/08
CPC分类号： G06F21/602 , G06F21/606 , G06F21/76 , H04L9/0841 , H04L9/30 , H04L9/3066 , H04L2209/80
摘要： An apparatus having a first memory circuit, a plurality of arithmetic modules, and a plurality of second memory circuits. The first memory circuit may be configured to read or write data to or from a host. The plurality of arithmetic modules each may be configured to be enabled or disabled in response to control signals received from the first memory circuit. The plurality of second memory circuits may be configured to read or write data to or from the first memory circuit through a data exchange layer. The arithmetic modules provide cryptographic protection of the data.
摘要翻译：一种具有第一存储器电路，多个运算模块和多个第二存储器电路的装置。第一存储器电路可以被配置为向或从主机读取或写入数据。多个算术模块可以被配置为响应于从第一存储器电路接收的控制信号而被使能或禁用。多个第二存储器电路可以被配置为通过数据交换层向或从第一存储器电路读取数据或从第一存储器电路写入数据。算术模块提供数据的加密保护。

68. 发明授权

US09059189B2 Integrated circuit with electromagnetic energy anomaly detection and processing 有权
标题翻译：集成电路与电磁能异常检测与处理
公开(公告)号：US09059189B2
公开(公告)日：2015-06-16
申请号：US13410909
申请日：2012-03-02
申请人： Walter J. Keller, III , Bogdan A. Pathak
发明人： Walter J. Keller, III , Bogdan A. Pathak
IPC分类号： G08B13/14 , H01L23/00
CPC分类号： H04B1/26 , G06F21/44 , G06F21/76 , G06F21/87 , H01L23/576 , H01L23/66 , H01L2223/6677 , H01L2924/0002 , H01L2924/14 , H01L2924/19105 , H01L2924/00
摘要： An integrated circuit includes an antenna, a die manufactured from a semiconducting material, an RF energy collection and processing device disposed on or within the die and including at least a receiver and a processing device, an input configured to supply power to said RF energy collection and processing device and an output for operative communication by said RF energy collection and processing device. The integrated circuit is configurable and operable to provide at least one of electromagnetic emission anomaly detection, tamper detection, anti-tamper monitoring, degradation monitoring, health monitoring, counterfeit detection, software changes monitoring, firmware changes monitoring and monitoring of other RF energy anomalies.
摘要翻译：集成电路包括天线，由半导体材料制成的管芯，设置在管芯上或管芯内的RF能量收集和处理装置，并且至少包括接收器和处理器件，被配置为向所述RF能量收集器以及处理装置和用于由所述RF能量收集和处理装置进行操作通信的输出。集成电路是可配置和可操作的，以提供电磁发射异常检测，篡改检测，防篡改监测，劣化监测，健康监测，伪造检测，软件变化监测，固件更改监测和其他RF能量异常监测中的至少一个。

69. 发明申请

US20150084670A1 SONOS FPGA Architecture Having Fast Data Erase and Disable Feature 有权
标题翻译： SONOS FPGA架构具有快速数据擦除和禁用功能
公开(公告)号：US20150084670A1
公开(公告)日：2015-03-26
申请号：US14481943
申请日：2014-09-10
申请人： Microsemi SoC Corporation
发明人： John McCollum
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , G06F12/14 , G06F21/76 , H03K19/17752 , H03K19/1776 , H03K19/17772
摘要： A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power from the programmable logic core, and simultaneously programming the n-channel device and erasing the p-channel device in all cells.
摘要翻译：一种用于快速数据擦除FPGA的方法，包括由多个SONOS配置存储器单元控制的可编程逻辑核，每个SONOS配置存储单元包括与n沟道SONOS存储晶体管串联的p沟道SONOS存储晶体管，其包括检测篡改FPGA，断开与可编程逻辑内核的电源，同时编程n通道器件并擦除所有单元中的p沟道器件。

70. 发明申请

US20150067287A1 DISTRIBUTED DYNAMIC MEMORY MANAGEMENT UNIT (MMU)-BASED SECURE INTER-PROCESSOR COMMUNICATION 有权
标题翻译：分布式动态内存管理单元（MMU） - 安全的内部处理器通信
公开(公告)号：US20150067287A1
公开(公告)日：2015-03-05
申请号：US14014288
申请日：2013-08-29
申请人： Qualcomm Incorporated
发明人： Azzedine Touzni , Thomas Tzeng
IPC分类号： G06F12/14
CPC分类号： G06F21/606 , G06F12/1009 , G06F12/1475 , G06F12/1483 , G06F15/167 , G06F21/76 , G06F21/79 , G06F2212/1052
摘要： A first processor and a second processor are configured to communicate secure inter-processor communications (IPCs) with each other. The first processor effects secure IPCs and non-secure IPCs using a first memory management unit (MMU) to route the secure and non-secure IPCs via a memory system. The first MMU accesses a first page table stored in the memory system to route the secure IPCs and accesses a second page table stored in the memory system to route the non-secure IPCs. The second processor effects at least secure IPCs using a second MMU to route the secure IPCs via the memory system. The second MMU accesses the second page table to route the secure IPCs.
摘要翻译：第一处理器和第二处理器被配置为彼此通信安全的处理器间通信（IPC）。第一个处理器使用第一个内存管理单元（MMU）通过内存系统对安全和非安全的IPC进行路由，从而影响安全的IPC和非安全的IPC。第一MMU访问存储在存储器系统中的第一页表以路由安全的IPC并访问存储在存储器系统中的第二页表以路由非安全的IPC。第二个处理器至少使用第二个MMU来保护安全的IPC，以便通过存储系统路由安全的IPC。第二个MMU访问第二页表以路由安全的IPC。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式