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61. 发明申请

US20120215984A1 HETEROGENEOUS PROCESSORS SHARING A COMMON CACHE 有权
标题翻译：共享缓存的异构处理器
公开(公告)号：US20120215984A1
公开(公告)日：2012-08-23
申请号：US13405798
申请日：2012-02-27
申请人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
发明人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享缓存的多核处理器。

62. 发明授权

US08156285B2 Heterogeneous processors sharing a common cache 有权
标题翻译：共享共享缓存的异构处理器
公开(公告)号：US08156285B2
公开(公告)日：2012-04-10
申请号：US12459683
申请日：2009-07-06
申请人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
发明人： Frank T. Hady , Mason B. Cabot , John Beck , Mark B. Rosenbluth
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0893 , G06F13/4022 , G06F13/4282 , G06F15/167 , G06F15/781 , G06F15/7842 , G06F15/7846 , G06F2212/283 , G06F2212/302 , G06F2212/314 , G06F2212/621
摘要： A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
摘要翻译：提出了一种提供异构处理器内核和共享缓存的多核处理器。

63. 发明申请

US20120082171A1 SINGLE CHIP PROTOCOL CONVERTER 有权
标题翻译：单芯片协议转换器
公开(公告)号：US20120082171A1
公开(公告)日：2012-04-05
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04L12/00
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

64. 发明授权

US08149702B2 Multi-mode bit rate processor 有权
标题翻译：多模比特率处理器
公开(公告)号：US08149702B2
公开(公告)日：2012-04-03
申请号：US12199640
申请日：2008-08-27
申请人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
发明人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
IPC分类号： H04J1/16
CPC分类号： G06F15/7842 , H04L1/0045 , H04L1/0052 , H04L1/1829
摘要： An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
摘要翻译：一种用于在无线系统中处理信号的装置包括用于从一组物理信道接收输入数据的第一存储器模块，用于处理输入数据的第一多个子模块。第一多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收经处理的输入数据和输出中间数据的第二存储器模块。第二存储器中的输入数据的位置与数据和传输通道规范相关联地被分配。该装置还包括用于处理中间数据的第二多个子模块。第二多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收和输出比特率处理输出的第三存储器模块。

65. 发明申请

US20120036337A1 Processor on an Electronic Microchip Comprising a Hardware Real-Time Monitor 审中-公开
标题翻译：包括硬件实时监视器在内的Microchip的处理器
公开(公告)号：US20120036337A1
公开(公告)日：2012-02-09
申请号：US13155260
申请日：2011-06-07
申请人： Philippe GROSSI
发明人： Philippe GROSSI
IPC分类号： G06F9/302 , G06F9/38
CPC分类号： G06F9/4881 , G06F9/5016 , G06F15/7842
摘要： A processor on an electronic microchip is capable of executing mathematical processes, each of said processes being associated with a priority, and includes means for the management of the processes, the means for the management of the processes taking the form of hardware, the management of the processes comprising the activation and the suspension of the processes and the management of the execution of the processes according to their priorities.
摘要翻译：电子微芯片上的处理器能够执行数学过程，每个所述过程与优先级相关联，并且包括用于管理过程的装置，用于以硬件形式管理过程的手段，管理这些过程包括根据其优先级激活和暂停过程以及管理进程的执行。

66. 发明授权

US08108661B2 Data processing apparatus and method of controlling the data processing apparatus 有权
标题翻译：数据处理装置及数据处理装置的控制方法
公开(公告)号：US08108661B2
公开(公告)日：2012-01-31
申请号：US12385265
申请日：2009-04-02
申请人： Won Jong Lee , Chan Min Park , Shi Hwa Lee
发明人： Won Jong Lee , Chan Min Park , Shi Hwa Lee
IPC分类号： G06F9/305 , G06F9/50 , G06F15/76
CPC分类号： G06F15/7842
摘要： Provided are a data processing apparatus and a method of controlling the data processing apparatus. The data processing apparatus may select a single stream processor from a plurality of stream processors based on stream processor status information, and input data into the selected stream processor. The stream processor status information may include first status information of a processor core and second status information of at least one internal memory.
摘要翻译：提供了一种数据处理装置和控制数据处理装置的方法。数据处理装置可以基于流处理器状态信息从多个流处理器中选择单流处理器，并将数据输入到所选择的流处理器中。流处理器状态信息可以包括处理器核心的第一状态信息和至少一个内部存储器的第二状态信息。

67. 发明申请

US20110145909A1 Interface Logic For A Multi-Core System-On-A-Chip (SoC) 失效
标题翻译：多核系统芯片（SoC）的接口逻辑
公开(公告)号：US20110145909A1
公开(公告)日：2011-06-16
申请号：US12639258
申请日：2009-12-16
申请人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
发明人： Ramana Rachakonda , Lance E. Hacking , Mahesh K. Reddy , Lori R. Borger , Chee Hak Teh , Pawitter P. Bhatia , John P. Lee
IPC分类号： G06F21/22
CPC分类号： G06F13/40 , G01R31/318572 , G06F15/7807 , G06F15/7842 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二核心的系统级芯片（SoC），耦合到核心的接口逻辑，耦合到接口逻辑的芯片组逻辑以及耦合在芯片组逻辑之间的虚拟防火墙逻辑和第二核心。接口逻辑可以包括防火墙逻辑，总线逻辑和测试逻辑，并且芯片组逻辑可以包括存储器控制器以提供与耦合到SoC的存储器的通信。在一些系统实现中，无论是在测试操作还是功能操作期间，在正常操作期间可以禁用第二个内核以提供单个核心SoC，从而在许多不同实现中使SoC的灵活性更高。描述和要求保护其他实施例。

68. 发明申请

US20110119322A1 On-Chip Networks for Flexible Three-Dimensional Chip Integration 有权
标题翻译：用于灵活三维芯片集成的片上网络
公开(公告)号：US20110119322A1
公开(公告)日：2011-05-19
申请号：US12617859
申请日：2009-11-13
申请人： Jian Li , Steven P. VanderWiel , Lixin Zhang
发明人： Jian Li , Steven P. VanderWiel , Lixin Zhang
IPC分类号： G06F15/16
CPC分类号： G06F15/7842
摘要： Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer.
摘要翻译：提供具有多个独立和协作的片上网络的具有三维集成电路器件的互连层的机构。关于实现互连层的装置，这种装置包括包含一个或多个第一功能单元和耦合到第一集成电路层的互连层的第一集成电路层。第一集成电路层和互连层彼此集成为单个三维集成电路。互连层包括多个独立的片上通信网络，这些独立的片上通信网络是独立可操作的并且独立地能够通电和关断，每个片上通信网络包括多个点对点通信链路，多个点对点通信链路通过多个连接点。一个或多个第一功能单元耦合到互连层的第一独立片上通信网络。

69. 发明授权

US07849291B2 Method and apparatus for performing improved group instructions 有权
标题翻译：用于执行改进的组指令的方法和装置
公开(公告)号：US07849291B2
公开(公告)日：2010-12-07
申请号：US11842038
申请日：2007-10-29
申请人： Craig Hansen , John Moussouris
发明人： Craig Hansen , John Moussouris
IPC分类号： G06F9/302
CPC分类号： G06F9/3802 , G06F9/30 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30072 , G06F9/30087 , G06F9/30145 , G06F9/3867 , G06F9/3869 , G06F12/0875 , G06F12/1027 , G06F15/7832 , G06F15/7842 , G06F2212/2515 , H04N21/2365 , H04N21/238 , H04N21/23805 , H04N21/4347 , Y02D10/13
摘要： Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.
摘要翻译：提出了一种系统和装置，其涉及包括执行单元的可编程处理器，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行多个不同的组浮点和组整数算术运算，每个算术运算在寄存器文件中的多个数据元素存储的寄存器上产生返回到寄存器文件中的寄存器的连接结果，其中，连接结果包括多个单独的结果其中，所述执行单元能够执行响应于数据处理指令以不同方式重新布置数据元素的组数据处理操作。

70. 发明申请

US20100180195A1 METHOD AND APPARATUS FOR HARDWARE XML ACCELERATION 有权
标题翻译：硬件XML加速的方法和装置
公开(公告)号：US20100180195A1
公开(公告)日：2010-07-15
申请号：US12730869
申请日：2010-03-24
申请人： Jochen Behrens , Marcelino M. Dignum , Wayne F. Seltzer , William T. Zaumen , John P. Petry , Santiago M. Pericas-Geertsen , Biswadeep Nag
发明人： Jochen Behrens , Marcelino M. Dignum , Wayne F. Seltzer , William T. Zaumen , John P. Petry , Santiago M. Pericas-Geertsen , Biswadeep Nag
IPC分类号： G06F17/00
CPC分类号： G06F15/7842
摘要： A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g., memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput.
摘要翻译：一种用于加速结构化文档处理的方法和装置。硬件XML加速器包括一个或多个处理器（例如，CMT处理器），一个或多个硬件XML解析器单元，一个或多个密码单元和各种接口（例如，到存储器，网络，通信总线）。 XML文档可以被整体处理，或者可以被分段（例如，被接收）来解析。解析器单元按字符逐个解析文档或段，验证字符，从文档汇编令牌，提取数据，生成令牌标题（描述令牌和数据），并转发令牌标题和数据以供应用程序消费。加密单元可以通过提供加密/解密功能，计算数字签名等来实施Web安全性，XML安全性或某些其他安全性方案。软件处理，总线利用和延迟（例如，存储器，总线）大大降低，从而显着提供改进的XML处理和安全处理吞吐量。

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