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61. 发明申请

US20140258799A1 IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION 审中-公开
标题翻译： IP核设计支持用户添加扫描注册选项
公开(公告)号：US20140258799A1
公开(公告)日：2014-09-11
申请号：US14281189
申请日：2014-05-19
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318541 , G01R31/318555 , G01R31/318586
摘要： An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
摘要翻译：集成电路具有知识产权核心。知识产权核心包括测试访问端口39，测试数据输入引线15，测试数据输出引线13，控制引线17和存在的外部寄存器ERP导线37.扫描寄存器25包含知识产权核心和ERP引导线37携带指示存在扫描寄存器的信号。

62. 发明授权

US08803581B2 Fast flip-flop structure with reduced set-up time 有权
标题翻译：快速的触发器结构，缩短设置时间
公开(公告)号：US08803581B2
公开(公告)日：2014-08-12
申请号：US12758451
申请日：2010-04-12
申请人： Shyh-An Chi , Shiue Tsong Shen , Jeff Lee , Frank Y. Lee
发明人： Shyh-An Chi , Shiue Tsong Shen , Jeff Lee , Frank Y. Lee
IPC分类号： H03K3/289 , H03K3/012
CPC分类号： H03K3/012 , G01R31/318541
摘要： A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.
摘要翻译：提供了一种具有缩短设置时间的触发器结构。触发器包括通过由时钟信号控制的第一开关接收功能数据的第一主锁存器，第二主锁存器通过由时钟信号控制的第二开关接收扫描数据，以及从锁存器连接到第一主器件通过由时钟信号控制的第三开关锁存。第二主锁存器通过由扫描使能信号控制的第四开关耦合到第一主锁存器，使得扫描使能信号控制功能数据或扫描数据是否变为从第一主锁存器到从锁存器的输出，以及从锁存器用于锁存和传输来自第一主锁存器的输出。

63. 发明申请

US20140189453A1 HIGH DENSITY LOW POWER SCAN FLIP-FLOP 有权
标题翻译：高密度低功率扫描FLIP-FLOP
公开(公告)号：US20140189453A1
公开(公告)日：2014-07-03
申请号：US14107932
申请日：2013-12-16
申请人： Texas Instruments Incorporated
发明人： Girishankar Gurumurthy
IPC分类号： G01R31/3177
CPC分类号： G01R31/318541 , G01R31/318575
摘要： A scan flip flop includes a partial multiplexer coupled to a master latch. The partial multiplexer is configured to receive a scan enable (SCAN) where the partial multiplexer includes an OR gate coupled to a tri-stated AND gate. A tri-state inverter is coupled to an output of the master latch and a slave latch is configured to receive an output of the tri-state inverter. A delay element is coupled to the slave latch, where the delay element is configured to delay a first output of the slave latch in response to the scan enable to generate a dedicated scan output.
摘要翻译：扫描触发器包括耦合到主锁存器的部分多路复用器。部分多路复用器被配置为接收扫描使能（SCAN），其中部分多路复用器包括耦合到三态和门的或门。三态逆变器耦合到主锁存器的输出，并且从锁存器被配置为接收三态反相器的输出。延迟元件耦合到从锁存器，其中延迟元件被配置为响应于扫描使能来延迟从锁存器的第一输出以产生专用扫描输出。

64. 发明申请

US20140157071A1 LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS 审中-公开
标题翻译：低功耗扫描和延迟测试方法和设备
公开(公告)号：US20140157071A1
公开(公告)日：2014-06-05
申请号：US14173492
申请日：2014-02-05
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel , Joel J. Graber
IPC分类号： G01R31/3185
CPC分类号： G01R31/318544 , G01R31/31721 , G01R31/3177 , G01R31/318541 , G01R31/318547 , G01R31/318575 , G01R31/31858 , G01R31/318586
摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
摘要翻译：扫描和扫描BIST架构通常用于测试集成电路中的数字电路。本公开改进了低功率扫描和扫描BIST方法。该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

65. 发明授权

US08732499B2 State retention circuit adapted to allow its state integrity to be verified 有权
标题翻译：状态保持电路适于允许其状态完整性被验证
公开(公告)号：US08732499B2
公开(公告)日：2014-05-20
申请号：US13067395
申请日：2011-05-27
申请人： David Walter Flynn
发明人： David Walter Flynn
IPC分类号： G06F1/32
CPC分类号： G01R31/318541 , G06F1/3237 , G06F1/3296 , G06F11/10 , G06F11/2236
摘要： A state retention component is provided which is configured to form part of data processing circuitry. The state retention component is configured to hold a state value at a node of the data processing circuitry when the data processing circuitry enters a low power mode. The state retention component comprises a scan input, wherein the state retention component configured, when a scan enable signal is asserted, to read in the state value from a scan input value applied at the scan input, and a scan output, wherein the state retention component is configured, when the scan enable signal is asserted, to read out the state value to the scan output. When the scan enable signal is not asserted, the state retention circuit outputs at the scan output a parity value, wherein the parity value is generated by combinatorial function circuitry on the basis of the state value and the scan input value, wherein the combinatorial function circuitry is configured such that the parity value inverts if either the state value or the scan input value changes, thus providing an external indication of the integrity of the state value held by the state retention component.
摘要翻译：提供状态保持组件，其被配置为形成数据处理电路的一部分。状态保持组件被配置为当数据处理电路进入低功率模式时，在数据处理电路的节点处保持状态值。状态保持部件包括扫描输入，其中状态保持部件被配置为当扫描使能信号被断言时，从在扫描输入处施加的扫描输入值读取状态值和扫描输出，其中状态保持当扫描启用信号被置位时，组件被配置为将扫描输出的状态值读出。当扫描使能信号未被置位时，状态保持电路在扫描输出端输出奇偶校验值，其中奇偶校验值由组合函数电路基于状态值和扫描输入值产生，其中组合函数电路被配置为使得如果状态值或扫描输入值改变，则奇偶校验值反转，从而提供由状态保持组件保持的状态值的完整性的外部指示。

66. 发明授权

US08726109B2 Architecture, system, method, and computer-accessible medium for eliminating scan performance penalty 有权
标题翻译：架构，系统，方法和计算机可访问介质，可消除扫描性能损失
公开(公告)号：US08726109B2
公开(公告)日：2014-05-13
申请号：US13462139
申请日：2012-05-02
申请人： Ozgur Sinanoglu
发明人： Ozgur Sinanoglu
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： Exemplary apparatus, methods, and computer-accessible medium can be provided for transforming a circuit. For example, it is possible to select, from the circuit, at least one scan cell which includes a first multiplexer coupled to a first flip-flop. A second flip-flop and a second multiplexer can be inserted in the circuit. The first multiplexer can be coupled as an input to the second flip-flop, and the second multiplexer can be coupled to the output of the first flip-flop and the second flip-flop.
摘要翻译：可以提供示例性的装置，方法和计算机可访问介质来转换电路。例如，可以从电路中选择包括耦合到第一触发器的第一多路复用器的至少一个扫描单元。电路中可以插入第二触发器和第二多路复用器。第一多路复用器可以作为第二触发器的输入耦合，并且第二多路复用器可以耦合到第一触发器和第二触发器的输出。

67. 发明申请

US20140129887A1 FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN INPUT 有权
标题翻译：对于扫描输入，具有减少保持时间要求的FLIP-FLOP电路
公开(公告)号：US20140129887A1
公开(公告)日：2014-05-08
申请号：US13668143
申请日：2012-11-02
申请人： NVIDIA CORPORATION
发明人： Hwong-Kwo Lin , Ge Yang , Xi Zhang , Jiani Yu , Ting-Hsiang Chu
IPC分类号： G01R31/3177
CPC分类号： G01R31/318541 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318594
摘要： A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.
摘要翻译：扫描触发电路包括扫描输入子电路和选择子电路。扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号信号在两个不同的逻辑电平之间。选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相形式输出为第一选择输入信号。

68. 发明授权

US08667349B2 Scan flip-flop circuit having fast setup time 有权
标题翻译：具有快速建立时间的扫描触发器电路
公开(公告)号：US08667349B2
公开(公告)日：2014-03-04
申请号：US13207494
申请日：2011-08-11
申请人： Shang-Chih Hsieh , Chih-Chiang Chang , Chang-Yu Wu
发明人： Shang-Chih Hsieh , Chih-Chiang Chang , Chang-Yu Wu
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.
摘要翻译：扫描触发器电路包括用于向数据节点提供数据信号的输入级，其中输入级包括耦合到数据节点的晶体管器件的第一和第二堆叠。第一堆栈在用于输入到数据节点的正常操作模式期间接收数据输入信号，并且第二堆栈在用于输入到数据节点的扫描测试模式期间接收扫描输入信号。扫描触发器电路还包括直接耦合到数据节点的主锁存器，用于锁存来自输入级的数据信号并输出数据信号; 耦合到主锁存器的输出的从锁存器，用于锁存来自主锁存器的输出并输出该输出; 以及扫描和时钟控制逻辑模块。扫描和时钟控制逻辑模块控制第一个堆栈，以在正常操作模式下将数据输入信号输入到数据节点。

69. 发明申请

US20140055158A1 Integrated Circuit Die Having Input and Output Circuit Pads, Test Circuitry, and Multiplex Circuitry 有权
标题翻译：具有输入和输出电路板，测试电路和多路复用电路的集成电路芯片
公开(公告)号：US20140055158A1
公开(公告)日：2014-02-27
申请号：US14068819
申请日：2013-10-31
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel , Alan Hales
IPC分类号： G01R1/073
CPC分类号： G01R31/3177 , G01R1/07342 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318547 , G01R31/318555 , G01R31/318558 , G01R31/318563 , G01R31/318566 , G01R31/318572 , G01R31/31924 , G01R31/31926
摘要： Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
摘要翻译：位于半导体管芯上的测试电路使得测试仪能够通过将激励和响应模式输入到多个管芯/ IC来并行地测试多个管芯/ IC。来自测试器的响应模式与待比较的芯片/ IC的输出响应一起输入到测试电路。还公开了使用响应信号编码方案，其中测试者使用每个测试电路的单个信号向测试电路发送响应测试命令，以执行：（1）比较管芯/ IC输出与期望的逻辑高（ 2）比较管芯/ IC输出与预期逻辑低电平，以及（3）掩模比较操作。信号编码方案的使用允许对芯片和IC进行功能测试，因为每个管芯/ IC输出所需的所有响应测试命令（即1-3以上）可以仅使用单个测试仪信号连接传输到每个管芯/ IC输出芯片/ IC输出。除功能测试外，还可以对芯片和IC进行扫描测试。

70. 发明申请

US20140028362A1 INPUT CIRCUIT 有权
标题翻译：输入电路
公开(公告)号：US20140028362A1
公开(公告)日：2014-01-30
申请号：US14040519
申请日：2013-09-27
申请人： PANASONIC CORPORATION
发明人： Tsuyoshi KOIKE , Shigeo HOUMURA
IPC分类号： H03K3/037
CPC分类号： H03K3/0375 , G01R31/318541 , G11C29/1201 , G11C29/32 , G11C2029/3202
摘要： A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.
摘要翻译：组合电路分别根据第一和第二输入信号产生第一和第二内部信号。第一主锁存电路选择性地捕获并保持扫描信号和第一内部信号，并且基于这样捕获和保持的信号产生第一输出信号和第一中间信号。第一从锁存电路选择性地捕获并保持第一中间信号和第二内部信号，并且基于如此捕获和保持的信号产生第二输出信号和扫描输出信号。这种布置减少了应用扫描路径测试方法的半导体集成电路中提供的输入电路的电路规模和功耗。

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