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61. 发明授权

US5974519A Address re-designate circuit for microcontroller 失效
标题翻译：微控制器地址重新指定电路
公开(公告)号：US5974519A
公开(公告)日：1999-10-26
申请号：US865935
申请日：1997-05-30
申请人： Dong-Soo Cho
发明人： Dong-Soo Cho
IPC分类号： G06F13/14 , G06F12/02 , G06F12/06 , G06F12/10
CPC分类号： G06F12/0653
摘要： An improved address re-designate circuit for a programmable microcontroller which is capable of arbitrarily selecting a peripheral circuit and re-designating an address corresponding to the selected peripheral circuit has the advantage of easily being programmed since the user can arbitrarily select a peripheral circuit disposed in the microcontroller chip according to a desired function and can re-designate an address thereof.
摘要翻译：一种用于可编程微控制器的改进的地址重新指定电路，其能够任意选择外围电路并重新指定与所选择的外围电路对应的地址，具有易于编程的优点，因为用户可以任意选择设置在微控制器芯片根据期望的功能并且可以重新指定其地址。

62. 发明授权

US5970114A X-ray mask and its fabrication method 失效
标题翻译： X射线掩模及其制造方法
公开(公告)号：US5970114A
公开(公告)日：1999-10-19
申请号：US919812
申请日：1997-08-29
申请人： Don-Hee Lee , Ki-Chang Song , Young-Sam Jeon , Chil-Keun Park
发明人： Don-Hee Lee , Ki-Chang Song , Young-Sam Jeon , Chil-Keun Park
IPC分类号： G03F1/22 , H01L21/027 , G21K5/00
CPC分类号： G03F1/22
摘要： Disclosed are X-ray masks exhibiting improved stability and reliability of the X-ray masks, and methods of making these masks. The X-ray masks include a membrane, an X-ray absorber pattern on the membrane, which is formed on a top side of a substrate, or an oxide layer between the membrane and the X-ray absorber pattern.
摘要翻译：公开了显示出提高X射线掩模的稳定性和可靠性的X射线掩模以及制造这些掩模的方法。 X射线掩模包括膜，膜上的X射线吸收体图案，其形成在衬底的顶侧，或膜与X射线吸收体图案之间的氧化物层。

63. 发明授权

US5966609A Method of fabricating dome-shaped semiconductor device 失效
标题翻译：制造圆顶形半导体器件的方法
公开(公告)号：US5966609A
公开(公告)日：1999-10-12
申请号：US974464
申请日：1997-11-20
申请人： Jae-Soon Kwon
发明人： Jae-Soon Kwon
IPC分类号： H01L29/78 , H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10876 , H01L28/82 , H01L27/10811 , H01L27/10823
摘要： A semiconductor device and a fabrication method thereof which are capable of enhancing the electrostatic capacity of a capacitor and preventing a short channel effect which occurs due to the decrease of a channel width. The semiconductor device includes a semiconductor substrate having a protrusion, a first insulation film formed on a lateral surface of the protrusion and on the semiconductor substrate neighboring with the protrusion, a conductive type sidewall spacer formed on the first insulation film, a first dopant region formed on an upper surface of the protrusion, a second dopant region formed in the semiconductor substrate in an outer portion from the conductive type sidewall spacer, an insulation film pattern formed on a surface of the conductive type sidewall spacer, a first conductive layer pattern contacting with the second dopant region and formed on the insulation film pattern, an interlayer insulation layer formed on an upper surface of the first conductive layer pattern, and a second conductive layer pattern formed on the interlayer insulation layer.
摘要翻译：一种半导体器件及其制造方法，其能够增强电容器的静电容量并防止由于沟道宽度的减小而发生的短沟道效应。该半导体器件包括具有突起的半导体衬底，形成在突起的侧表面上的与突出部相邻的半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的导电型侧壁间隔物，形成第一掺杂区域在所述突起的上表面上形成在所述半导体衬底中的从所述导电型侧壁间隔物的外部的第二掺杂剂区域，形成在所述导电型侧壁间隔物的表面上的绝缘膜图案，与所述第二掺杂剂区域形成在所述绝缘膜图案上，形成在所述第一导电层图案的上表面上的层间绝缘层和形成在所述层间绝缘层上的第二导电层图案。

64. 发明授权

US5963796A Fabrication method for semiconductor package substrate and semiconductor package 失效
标题翻译：半导体封装基板和半导体封装的制造方法
公开(公告)号：US5963796A
公开(公告)日：1999-10-05
申请号：US27185
申请日：1998-02-20
申请人： Sun Dong Kim
发明人： Sun Dong Kim
IPC分类号： H01L23/24 , H01L23/367 , H01L23/498 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/24 , H01L23/3677 , H01L23/49822 , H01L23/49861 , H01L2224/451 , H01L2224/48247 , H01L2224/49171 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00013 , H01L2924/00014 , H01L2924/181
摘要： A fabrication method for a chip package includes the steps of forming a first substrate having embedded leads, forming a second substrate with embedded leads and a central aperture therethrough, and attaching the second substrate to the first substrate to form a substrate with a recess for receiving a chip. A chip may then be mounted within the central aperture of the second substrate, on the first substrate, and bond pads of the chip may be attached to leads exposed on one of the first and second substrates with a plurality of metal wires. A resin may be molded over the device to protect the metal wires, the chip, and the leads.
摘要翻译：芯片封装的制造方法包括以下步骤：形成具有嵌入引线的第一衬底，形成具有嵌入引线的第二衬底和穿过其的中心孔，以及将第二衬底附接到第一衬底以形成具有用于接收的凹部的衬底一个芯片然后可以将芯片安装在第二基板的中心孔中，在第一基板上，并且芯片的接合焊盘可以用多个金属线连接到暴露在第一和第二基板之一上的引线上。可以在器件上模制树脂以保护金属线，芯片和引线。

65. 发明授权

US5958270A Wire bonding wedge tool with electric heater 失效
标题翻译：带电加热器的电线楔形工具
公开(公告)号：US5958270A
公开(公告)日：1999-09-28
申请号：US589678
申请日：1996-01-22
申请人： Jae Weon Cho
发明人： Jae Weon Cho
IPC分类号： H01L21/60 , B23K20/00 , H05B1/00
CPC分类号： H01L24/85 , B23K20/004 , H01L24/78 , H01L2224/45124 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48472 , H01L2224/78313 , H01L2224/78318 , H01L2224/85181 , H01L2224/85205 , H01L24/45 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/15153 , H01L2924/15165
摘要： In a wedge tool having a heating device, a metal rod having a heating line, a conductive wire or a thin film-type heating plate is disposed at a predetermined portion of the wedge tool, to which power is supplied through a power supply unit, respectively, in order to provide heat to the wedge tool in wire bonding process. By having such a construction, the wedge tool has the heating system for generating heat, so that a substantially preferable and remarkable bonding force can be obtained.
摘要翻译：在具有加热装置的楔形工具中，具有加热线的金属杆，导线或薄膜型加热板设置在通过电源单元供电的楔形工具的预定部分处，以便在引线接合过程中向楔形工具提供热量。通过这样的结构，楔形工具具有用于产生热的加热系统，从而可以获得基本上优选和显着的结合力。

66. 发明授权

US5953602A EEPROM cell and related method of making thereof 失效
标题翻译： EEPROM单元具有改进的拓扑结构和减少的漏电流
公开(公告)号：US5953602A
公开(公告)日：1999-09-14
申请号：US978028
申请日：1997-11-25
申请人： Han Su Oh , Jang Han Kim
发明人： Han Su Oh , Jang Han Kim
IPC分类号： H01L21/336 , H01L29/423 , H01L29/788 , H01L21/8238
CPC分类号： H01L29/66825 , H01L29/42336 , H01L29/7883
摘要： An EEPROM cell of reduced leakage current during erasure and improved cell topology includes a first conductivity type substrate having a channel region, a trench formed in the channel region of the substrate, first spacers formed on opposed sidewalls of the trench, and a gate oxide film formed at the bottom of the trench between the first spacers. Second conductivity type source/drain regions are formed in the substrate at opposite side of the trench. A tunneling oxide film is further provided on the substrate overlying the drain region and proximate the trench. An insulation film is provided over the entire substrate surface except the trench and the tunneling oxide film. In addition, a floating gate is formed on the insulation film over the source and drain regions, as well as the gate oxide film at the trench bottom. Second spacers are provided on the insulation film at opposed side surfaces of the floating gate. A dielectric film is then provided on the surface of the floating gate and the second spacers, and a control gate is formed on the dielectric film.
摘要翻译：在擦除期间减小的漏电流和改进的电池拓扑的EEPROM单元包括具有沟道区的第一导电型衬底，形成在衬底的沟道区中的沟槽，形成在沟槽的相对侧壁上的第一衬垫和栅氧化膜形成在第一间隔物之间的沟槽的底部。在沟槽的相对侧的衬底中形成第二导电类型的源极/漏极区域。隧道氧化膜还设置在衬底上，覆盖漏极区域并且靠近沟槽。除了沟槽和隧道氧化物膜之外，在整个衬底表面上提供绝缘膜。此外，在源极和漏极区域上的绝缘膜上以及沟槽底部的栅极氧化物膜上形成浮栅。第二间隔件设置在浮动栅极的相对侧表面处的绝缘膜上。然后在浮置栅极和第二间隔物的表面上提供电介质膜，并且在电介质膜上形成控制栅极。

67. 发明授权

US5949705A DRAM cell, DRAM and method for fabricating the same 失效
公开(公告)号：US5949705A
公开(公告)日：1999-09-07
申请号：US035841
申请日：1998-03-06
申请人： Young Kwon Jun , Yoo Chan Jeon
发明人： Young Kwon Jun , Yoo Chan Jeon
IPC分类号： G11C11/401 , G11C11/402 , G11C11/404 , G11C11/4074 , H01L21/8242 , H01L27/108 , G11C11/24 , G11C11/34
CPC分类号： G11C11/4074 , G11C11/404 , H01L27/108
摘要： The DRAM cell includes a first transistor, a second transistor, and a capacitor. The first and second transistors each have a gate, a source, and a drain electrode. The gate electrode of the second transistor is connected to one of the source and drain electrodes of the first transistor, and a first electrode of the capacitor is connected to the gate electrode of the second transistor. Also, a second electrode of the capacitor is connected to one of the source and drain electrodes of the second transistor. One of the source and drain electrodes of the second transistor not connected to the second electrode of the capacitor is connected to the gate electrode of the second transistor. Accordingly, the second transistor is on when a logic value of "1" is stored in the gate thereof, and off when a logic value of `0` is stored in the gate thereof. A wordline is connected to the gate electrode of the first transistor, a bitline is connected to the one of the source and drain electrodes of the first transistor not connected to the gate of the second transistor, and a reading line is connected to the second electrode of the capacitor. By applying a voltage corresponding to a logic value to the bitline, and selectively turning on the writing wordline, the logic value on the bitline is stored in the gate electrode of the second transistor. During a reading operation, a reference voltage is applied to the bitline, and a reading voltage is applied to the reading wordline. Then, the first transistor is selectively turned on by applying a voltage to the writing wordline. Based on the fluctuation in the reference voltage applied to the bitline, the logic value stored in the gate of the second transistor is easily determined.

68. 发明授权

US5945861A Clock signal modeling circuit with negative delay 失效
标题翻译：具有负延迟的时钟信号建模电路
公开(公告)号：US5945861A
公开(公告)日：1999-08-31
申请号：US873860
申请日：1997-06-12
申请人： Jae Goo Lee , Sung Man Park
发明人： Jae Goo Lee , Sung Man Park
IPC分类号： G06F1/10 , G11C7/22 , G11C11/407 , H03K5/13 , H03K5/135 , H03K5/14
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03K5/131 , H03K5/133 , H03K5/135
摘要： The circuit of the present invention prevents a multi-locking phenomenon, reduces power consumption and provides an accurately locked internal clock signal. A delay unit sequentially delays an external clock signal through a plurality of unit delay terminals. A sampling and computation unit maintains the levels of signals from the unit delay terminals connected after a predetermined unit delay terminal, in which a locking phenomenon occurs, to a predetermined level when a delay clock signal among a plurality of delay clock signals from the unit delay terminals is locked. An output unit outputs a delay clock signal locked to an external clock signal in accordance with an output from the sampling and computation unit.
摘要翻译：本发明的电路防止多锁现象，降低功耗并提供精确锁定的内部时钟信号。延迟单元通过多个单元延迟端子顺序地延迟外部时钟信号。采样和计算单元在来自单位延迟的多个延迟时钟信号中的延迟时钟信号之后，将来自发生锁定现象的预定单元延迟端子之后连接的单元延迟端子的信号电平维持在预定电平终端被锁定。输出单元根据采样和计算单元的输出输出锁定到外部时钟信号的延迟时钟信号。

69. 发明授权

US5945706A Memory device 失效
标题翻译：内存设备
公开(公告)号：US5945706A
公开(公告)日：1999-08-31
申请号：US30206
申请日：1998-02-25
申请人： Young-Kwon Jun
发明人： Young-Kwon Jun
IPC分类号： G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/788
CPC分类号： G11C11/404 , H01L27/108
摘要： A memory device and method of forming the same, includes a plurality of wordlines for applying a cell driving signal, a plurality of bitlines for inputting or outputting data, and a plurality of cells, each cell having a first gate, source and drain electrodes and a second gate, wherein either the first or second gate is connected to one of the wordlines, the source electrode is connected to one of the bitlines, and the drain electrode is connected to either the first or second gate which is not connected to the one wordline.
摘要翻译：存储器件及其形成方法包括用于施加单元驱动信号的多个字线，用于输入或输出数据的多个位线，以及多个单元，每个单元具有第一栅极，源极和漏极，以及第二栅极，其中第一栅极或第二栅极连接到字线之一，源电极连接到位线之一，漏电极连接到未连接到第一栅极的第一栅极或第二栅极字线

70. 发明授权

US5943289A Hierarchical word line structure 失效
标题翻译：分层字线结构
公开(公告)号：US5943289A
公开(公告)日：1999-08-24
申请号：US25111
申请日：1998-02-17
申请人： Jin-Hong Ahn , Jeong-Su Jeong
发明人： Jin-Hong Ahn , Jeong-Su Jeong
IPC分类号： G11C11/407 , G11C8/08 , G11C8/14 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C8/14 , G11C8/08
摘要： A hierarchical word line structure for a semiconductor memory is provided that substantially eliminates coupling noise between neighboring wiring lines by driving neighboring sub-word lines by different main word lines. The hierarchical word line structure further reduces a layout size. The hierarchical word line structure uses one less transistor than a related art sub-word line driver. The word line includes a plurality of word line rows that each include a plurality of sub-word line drivers. The sub-word line drivers receive sub-word line driver enable signals among which only one signal becomes high level at a time. Each of the word line rows correspond to a main word line and a subset of the plurality of sub-word line drivers that drive neighboring sub-word lines are coupled to different respective main word lines.
摘要翻译：提供一种用于半导体存储器的分层字线结构，通过用不同的主字线驱动相邻子字线，从而基本上消除了相邻布线之间的耦合噪声。分层字线结构进一步减少了布局尺寸。分层字线结构使用比现有技术的子字线驱动器少一个的晶体管。字线包括多个字线行，每行包括多个子字线驱动器。子字线驱动器接收子字线驱动器使能信号，其中一次只有一个信号变为高电平。每个字线行对应于主字线，并且驱动相邻子字线的多个子字线驱动器的子集耦合到不同的相应主字线。

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