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61. 发明授权

US09105559B2 Conformal doping for FinFET devices 有权
标题翻译： FinFET器件的共形掺杂
公开(公告)号：US09105559B2
公开(公告)日：2015-08-11
申请号：US14028517
申请日：2013-09-16
申请人： International Business Machines Corporation , GLOBALFOUNDRIES Inc.
发明人： Veeraraghavan S. Basker , Nathaniel Berliner , Hyun-Jin Cho , Johnathan Faltermeier , Kam-Leung Lee , Tenko Yamashita
IPC分类号： H01L21/00 , H01L21/18 , H01L21/225
CPC分类号： H01L21/18 , H01L21/2236 , H01L21/2251 , H01L21/845 , H01L29/66803
摘要： A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFET fins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.
摘要翻译：在包括NFET鳍片和PFET鳍片的半导体衬底上的FinFET器件的共形掺杂工艺。在第一示例性实施例中，N型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。将半导体衬底退火以将N型掺杂剂从N型掺杂剂组合物驱动到NFET鳍中。 P型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。将半导体衬底退火以将P型掺杂剂从P型掺杂剂组合物驱动到PFET鳍中。在第二示例性实施例中，NFET鳍和PFET鳍之一可以被第一掺杂剂组合物覆盖，然后第二掺杂剂组合物可以覆盖NFET鳍和PFET鳍，接着进行退火以在两种掺杂剂中驱动。

62. 发明申请

US20150179740A1 TRANSISTOR DEVICE WITH STRAINED LAYER 审中-公开
标题翻译：具有应变层的晶体管器件
公开(公告)号：US20150179740A1
公开(公告)日：2015-06-25
申请号：US14136420
申请日：2013-12-20
申请人： GLOBAL FOUNDRIES Inc.
发明人： Dina H. Triyoso , Elke Erben , Martin Trentzsch , Peter Moll , Roman Boschke
IPC分类号： H01L29/10 , H01L29/66 , H01L29/78
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66575 , H01L29/66628
摘要： A method for forming a transistor device is disclosed that includes forming a first gate electrode on a substrate, forming a nitride layer, in particular an SiN layer, over the first gate electrode and forming a first strained layer over the nitride layer, in particular the SiN layer. A transistor device is also disclosed that includes a first gate electrode, a nitride layer, in particular an SiN layer, formed over the first gate electrode and a first strained layer formed over the nitride layer, in particular the SiN layer.
摘要翻译：公开了一种用于形成晶体管器件的方法，其包括在衬底上形成第一栅电极，在第一栅电极上形成氮化物层，特别是SiN层，并在氮化物层上形成第一应变层，特别地， SiN层。还公开了一种晶体管器件，其包括形成在第一栅电极上方的第一栅电极，氮化物层，特别是SiN层，以及形成在氮化物层，特别是SiN层上的第一应变层。

63. 发明申请

US20150162439A1 SEMICONDUCTOR DEVICE INCLUDING A TRANSISTOR HAVING A LOW DOPED DRIFT REGION AND METHOD FOR THE FORMATION THEREOF 审中-公开
标题翻译：包括具有低DOPED DRIFT区域的晶体管的半导体器件及其形成方法
公开(公告)号：US20150162439A1
公开(公告)日：2015-06-11
申请号：US14099375
申请日：2013-12-06
申请人： Global Foundries Inc.
发明人： Jan Hoentschel , Ran Yan , Stefan Flachowsky , Sven Beyer
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/66431 , H01L29/66636 , H01L29/66659 , H01L29/66689 , H01L29/7835
摘要： An illustrative semiconductor device disclosed herein includes a semiconductor substrate. The semiconductor substrate includes a first semiconductor material. In the first semiconductor material, a recess is provided. The recess is filled with a second semiconductor material having a different composition than the first semiconductor material. The semiconductor device further includes a first transistor including a source region, a drain region, a gate electrode and a channel region below the gate electrode. The channel region is arranged at two or more laterally opposite sides of the drain region. The source region is arranged at two or more laterally opposite sides of the channel region. The drain region includes a low doped drift region and a highly doped region. A dopant concentration in the low doped drift region is at least one of smaller than a dopant concentration in the highly doped region and approximately zero. At least the low doped drift region is provided in the second semiconductor material.
摘要翻译：本文公开的说明性半导体器件包括半导体衬底。半导体衬底包括第一半导体材料。在第一半导体材料中，设置有凹部。凹部填充有与第一半导体材料不同的组成的第二半导体材料。半导体器件还包括第一晶体管，其包括源极区，漏极区，栅电极和栅极下方的沟道区。沟道区域布置在漏极区域的两个或更多个横向相对侧。源极区域布置在沟道区域的两个或更多个横向相对侧。漏区包括低掺杂漂移区和高掺杂区。低掺杂漂移区域中的掺杂剂浓度至少要小于高掺杂区域中的掺杂剂浓度，并且大约为零。至少在第二半导体材料中提供低掺杂漂移区。

64. 发明申请

US20150129933A1 TUCK STRATEGY IN TRANSISTOR MANUFACTURING FLOW 有权
标题翻译：晶闸管制造流程中的TUCK策略
公开(公告)号：US20150129933A1
公开(公告)日：2015-05-14
申请号：US14076562
申请日：2013-11-11
申请人： GLOBAL FOUNDRIES Inc.
发明人： Robert Lutz
IPC分类号： H01L29/78 , H01L29/66 , H01L21/762
CPC分类号： H01L29/7848 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/0692 , H01L29/66568 , H01L29/66636 , H01L29/7846
摘要： When forming field effect transistors with a semiconductor alloy layer, e.g., SiGe, embedded in the source/drain regions, a strategy called tucking has been developed in order to improve formation of the semiconductor alloy layer. An improved tucking strategy is hereby proposed, wherein the interface between the isolation region and the active region is not straight, but it rather defines an indentation, so that the active region protrudes into the isolation region in correspondence to the indentation. A gate is then formed on the surface of the device in such a way that a portion of the indentation is covered by the gate. An etching process is then performed, during which the gate acts as a screen. The etching thus gives rise to a cavity defined by a sidewall comprising portions exposing silicon, alternated to portions exposing the dielectric material of the isolation region.
摘要翻译：当用半导体合金层（例如嵌入在源/漏区中的SiGe）形成场效应晶体管时，已经开发了一种称为折叠的策略，以便改善半导体合金层的形成。因此，提出了一种改进的折叠策略，其中隔离区域和有源区域之间的界面不是直的，而是限定了凹陷，使得有源区域对应于凹陷突出到隔离区域中。然后在装置的表面上形成栅极，使得凹陷的一部分被栅极覆盖。然后执行蚀刻处理，在该过程期间，栅极用作屏幕。因此蚀刻产生由侧壁限定的空腔，该侧壁包括暴露硅的部分，交替地暴露隔离区的电介质材料的部分。

65. 发明授权

US09029956B2 SRAM cell with individual electrical device threshold control 有权
标题翻译：具有独立电气设备阈值控制的SRAM单元
公开(公告)号：US09029956B2
公开(公告)日：2015-05-12
申请号：US13282299
申请日：2011-10-26
申请人： Randy W. Mann , Scott D. Luning
发明人： Randy W. Mann , Scott D. Luning
IPC分类号： H01L27/11 , G11C11/00 , H01L27/02 , G11C11/412
CPC分类号： H01L27/0207 , G11C11/412 , H01L27/1104 , Y10S257/903
摘要： A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.
摘要翻译：提供了一种静态随机存取存储单元，其包括形成在基板上的第一和第二反相器，每个具有被配置为形成单元节点的上拉和下拉晶体管。第一和第二反相器的每个下拉晶体管驻留在掩埋氧化物层下方的第一区域上，并且具有第一掺杂水平和施加的偏压，为下拉晶体管提供第一电压阈值。一对通道晶体管耦合第一和第二反相器的单元节点，并且每一个形成在掩埋氧化物层下方的第二区域上，并且具有第二掺杂水平，并且施加的偏置为通路晶体管提供第二电压阈值。第一电压阈值与提供下拉晶体管和通道晶体管之间的电压阈值控制的第二电压阈值不同。

66. 发明申请

US20150076654A1 ENLARGED FIN TIP PROFILE FOR FINS OF A FIELD EFFECT TRANSISTOR (FINFET) DEVICE 审中-公开
标题翻译：用于场效应晶体管（FINFET）器件的放大的扩展鳍状剖面
公开(公告)号：US20150076654A1
公开(公告)日：2015-03-19
申请号：US14028728
申请日：2013-09-17
申请人： GLOBAL FOUNDRIES Inc.
发明人： Michael Ganz , Eric S. Kozarsky
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L21/76 , H01L21/3065 , H01L21/76224 , H01L29/66795 , H01L29/7853
摘要： Approaches for providing enlarged fin tips for a set of fins of a fin field effect transistor device (FinFET) are disclosed. Specifically, approaches are provided for patterning a hardmask formed over a substrate; forming a set of fin tips from the substrate using a first etch; and forming a set of fins from the substrate using a second etch, wherein each of the set of fin tips has a width greater than a most narrow section of each of the set of fins. Each of the fin tips has a tapered profile that enlarges towards a top end thereof to compensate for erosion losses during processing.
摘要翻译：公开了用于为翅片场效应晶体管器件（FinFET）的一组翅片提供扩大翅片尖端的方法。具体地，提供了用于对形成在衬底上的硬掩模进行图案化的方法; 使用第一蚀刻从衬底形成一组翅片尖端; 以及使用第二蚀刻从所述衬底形成一组翅片，其中所述一组翅片尖端中的每一个具有大于所述一组翅片中的每一个的最窄部分的宽度。每个翅片尖端具有朝向其顶端扩大的锥形轮廓，以补偿加工期间的冲蚀损失。

67. 发明申请

US20150035063A1 REDUCED SPACER THICKNESS IN SEMICONDUCTOR DEVICE FABRICATION 有权
标题翻译：半导体器件制造中减小的间隔厚度
公开(公告)号：US20150035063A1
公开(公告)日：2015-02-05
申请号：US13954530
申请日：2013-07-30
申请人： GLOBAL FOUNDRIES Inc
发明人： Juergen Faul , Frank Jakubowski
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L27/088 , H01L21/823425 , H01L21/823468 , H01L29/6656
摘要： In aspects of the present disclosure, a reliable encapsulation of a gate dielectric is provided at very early stages during fabrication. In other aspects, a semiconductor device is provided wherein a reliable encapsulation of a gate dielectric material is maintained, the reliable encapsulation being present at early stages during fabrication. In embodiments, a semiconductor device having a plurality of gate structures is provided over a surface of a semiconductor substrate. Sidewall spacers are formed over the surface and adjacent to each of the plurality of gate structures, wherein the sidewall spacers cover sidewall surfaces of each of the plurality of gate structures. After performing an implantation sequence into the sidewall spacers using adjacent gate structures as implantations masks, shadowing lower portions of the sidewall spacers, an etching process is performed for removing implanted portions from the sidewall spacers, leaving lower shadowed portions of the sidewall spacer as shaped sidewall spacers.
摘要翻译：在本公开的方面，在制造期间的非常早的阶段提供了栅极电介质的可靠封装。在其他方面，提供了一种半导体器件，其中保持了栅极电介质材料的可靠封装，可靠的封装存在于制造期间的早期阶段。在实施例中，在半导体衬底的表面上设置具有多个栅极结构的半导体器件。侧壁间隔件形成在表面上并且与多个栅极结构中的每一个相邻，其中侧壁间隔物覆盖多个栅极结构中的每一个的侧壁表面。在使用相邻栅极结构作为注入掩模的侧壁间隔件中进行植入序列之后，遮蔽侧壁间隔物的下部，执行蚀刻工艺以从侧壁间隔物去除植入部分，从而使侧壁间隔件的较低阴影部分成为成形侧壁间隔物

68. 发明授权

US08932934B2 Methods of self-forming barrier integration with pore stuffed ULK material 有权
标题翻译：自制成形障碍与孔填充ULK材料的方法
公开(公告)号：US08932934B2
公开(公告)日：2015-01-13
申请号：US13903283
申请日：2013-05-28
申请人： GlobalFoundries Inc.
发明人： Moosung M. Chae , Errol Todd Ryan , Nicholas Vincent Licausi , Christian Witt , Ailian Zhao , Ming He , Sean X. Lin , Xunyuan Zhang , Kunaljeet Tanwar
IPC分类号： H01L21/76 , H01L21/768 , H01L23/48 , H01L21/316 , H01L21/02
CPC分类号： H01L21/76831 , H01L21/02203 , H01L21/3105 , H01L21/31695 , H01L21/7682 , H01L21/76843 , H01L2221/1047
摘要： A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.
摘要翻译：提供了一种用于在半导体制造期间减少超低k层的自形成势垒的污染的方法的方法。一方面，一种方法包括：提供包含至少一个沟槽的固化的超低k膜，并且用孔填充材料填充膜的孔; 在沟槽的表面去除暴露的孔隙填充材料以形成暴露的孔; 并在沟槽的表面上形成自形成阻挡层。

69. 发明授权

US08869081B2 Automating integrated circuit device library generation in model based metrology 有权
标题翻译：在基于模型的计量学中自动化集成电路设备库生成
公开(公告)号：US08869081B2
公开(公告)日：2014-10-21
申请号：US13741645
申请日：2013-01-15
申请人： International Business Machines Corporation , GLOBALFOUNDRIES Inc.
发明人： Nedal Saleh , Alok Vaid
IPC分类号： G06F17/50
CPC分类号： H01L22/12 , G03F7/70625 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and running an IC library defining program using the chip design data in its original format and the user input data in its original format, the running of the IC library defining program including: determining a process variation for the at least one IC chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis.
摘要翻译：各种实施例包括用于生成用于散射分析的集成电路（IC）库的计算机实现的方法，计算机程序产品和系统。在某些情况下，方法包括：获得关于至少一个IC芯片的芯片设计数据; 获得关于所述至少一个IC芯片的用户输入数据; 并且使用其原始格式的芯片设计数据和其原始格式的用户输入数据运行IC库定义程序，IC库定义程序的运行包括：基于所述至少一个IC芯片确定所述至少一个IC芯片的处理变化芯片设计数据和用户输入数据; 将过程变化转换为形状变化数据; 并将文本格式的形状变化数据提供给用于散射分析的散点建模程序。

70. 发明申请

US20140264921A1 THROUGH-SILICON VIA WITH SIDEWALL AIR GAP 有权
标题翻译：通过硅胶空气通过硅橡胶
公开(公告)号：US20140264921A1
公开(公告)日：2014-09-18
申请号：US13853178
申请日：2013-03-29
申请人： GLOBAL FOUNDRIES Inc.
发明人： Shan Gao , Seung Man Choi
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L23/481 , H01L21/7682 , H01L21/76898 , H01L2224/11 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The sidewall air gap formation scheme for the TSV structure of disclosed embodiments reduces parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and serves to also reduce mechanical stress in silicon substrate surrounding the TSV conductor.
摘要翻译：本发明的实施例为通硅通（TSV）结构的侧壁处形成气隙提供了新颖的工艺集成。用于所公开实施例的TSV结构的侧壁气隙形成方案降低了衬底硅和TSV导体之间的寄生电容和耗尽区，并且还用于降低围绕TSV导体的硅衬底中的机械应力。

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