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61. 发明申请

US20070267703A1 STRAINED CHANNEL TRANSISTOR AND METHOD OF FABRICATION THEREOF 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US20070267703A1
公开(公告)日：2007-11-22
申请号：US11383951
申请日：2006-05-17
申请人： Yung Fu Chong , Zhijiong Luo , Judson Holt
发明人： Yung Fu Chong , Zhijiong Luo , Judson Holt
IPC分类号： H01L29/94
CPC分类号： H01L29/66628 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636
摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
摘要翻译：本发明涉及半导体集成电路。更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

62. 发明授权

US07297640B2 Method for reducing argon diffusion from high density plasma films 有权
标题翻译：降低高密度等离子体膜的氩扩散的方法
公开(公告)号：US07297640B2
公开(公告)日：2007-11-20
申请号：US11034952
申请日：2005-01-13
申请人： Jun Xie , Hoon Lian Yap , Chuin Boon Yeap , Weoi San Lok
发明人： Jun Xie , Hoon Lian Yap , Chuin Boon Yeap , Weoi San Lok
IPC分类号： H01L21/31
CPC分类号： H01L21/76801 , C23C16/045 , C23C16/401 , C23C16/45523 , H01L21/02164 , H01L21/02274 , H01L21/31612 , H01L21/31629 , H01L21/76837
摘要： A two-step high density plasma-CVD process is described wherein the argon content in the film is controlled by using two different argon concentrations in the argon/silane/oxygen gas mixture used for generating the high density plasma. The first step deposition uses high argon concentration and low sputter etch-to-deposition (E/D) ratio. High E/D ratio maintains the gap openings without necking. In the second step, a lower argon concentration and lower E/D ratio are used. Since observed metal defects are caused by argon diffusion in the top 200-300 nm of the HDP-CVD film, by controlling argon concentration in the top part of the film (i.e. second step deposition) to a low value, a reduced number of metal defects are achieved.
摘要翻译：描述了两步高密度等离子体CVD工艺，其中通过在用于产生高密度等离子体的氩/硅烷/氧气混合物中使用两种不同的氩浓度来控制膜中的氩含量。第一步沉积使用高氩浓度和低溅射蚀刻至沉积（E / D）比。高E / D比保持间隙开口没有颈缩。在第二步中，使用较低的氩浓度和较低的E / D比。由于观察到的金属缺陷是通过在HDP-CVD膜的顶部200-300nm的氩扩散引起的，通过将膜顶部的氩浓度（即第二级沉积）控制到低值，减少数量的金属实现了缺陷。

63. 发明申请

US20070264824A1 Methods to eliminate contact plug sidewall slit 有权
标题翻译：消除接触塞侧壁狭缝的方法
公开(公告)号：US20070264824A1
公开(公告)日：2007-11-15
申请号：US11434343
申请日：2006-05-15
申请人： Yong Siew , Beichao Zhang
发明人： Yong Siew , Beichao Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/76895 , H01L21/02074 , H01L21/7684 , H01L21/76852 , H01L21/76865 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed over the first barrier layer. The second barrier layer is comprised of TaN or WN. We planarize a first conductive layer to form a first contact plug in the contact hole. We reactive ion etch ( e.g., W touch up etch) the top surfaces using a Cl and B containing etch. Because of the composition of the barrier layers and RIE etch chemistry, the barrier layers are not significantly etched selectively to the dielectric layer. In a second embodiment, a barrier film is comprised of WN.
摘要翻译：使用接触式RIE形成阻挡层和接触塞的方法。在第一实施例中，我们在电介质层和接触孔中的衬底之间形成第一阻挡层。第一阻挡层由Ta构成。在第一阻挡层上形成第二阻挡层。第二阻挡层由TaN或WN构成。我们平面化第一导电层以在接触孔中形成第一接触塞。我们使用含Cl和B的蚀刻反应离子蚀刻（例如，W触摸上蚀刻）顶表面。由于阻挡层的组成和RIE蚀刻化学，阻挡层没有被有选择地蚀刻到电介质层。在第二实施例中，阻挡膜由WN构成。

64. 发明授权

US07294241B2 Method to form alpha phase Ta and its application to IC manufacturing 有权
标题翻译：形成α相Ta的方法及其在IC制造中的应用
公开(公告)号：US07294241B2
公开(公告)日：2007-11-13
申请号：US10336271
申请日：2003-01-03
申请人： Chim Seng Seet , Bei Chao Zhang , San Leong Liew , John Sudijono , Lai Lin Clare Yong
发明人： Chim Seng Seet , Bei Chao Zhang , San Leong Liew , John Sudijono , Lai Lin Clare Yong
IPC分类号： C23C14/34 , H01L21/44
CPC分类号： H01L21/76843 , C23C14/165 , C23C14/541 , H01L21/2855 , H01L21/76846 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05001 , H01L2224/0554 , H01L2224/13022 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/351 , Y10T428/12674 , Y10T428/12819 , Y10T428/12903 , H01L2924/00
摘要： A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.
摘要翻译：将由Al相Ta组成的Ta层溅射在Cu层上的方法。一个实施方案包括在低于200℃的衬底温度下在Cu表面上的Ta溅射沉积。另一个实施方案在Ta层溅射沉积之前具有在低于100℃的温度下的预冷却步骤。在另一个非限制性示例性实施例中，在钽溅射之前执行包括惰性气体溅射的预清洁步骤。另一非限制性示例实施例提供一种半导体结构，包括：半导体结构; 半导体结构上的铜层; 铜层上的钽层; 钽层包括α相Ta; 钽层上的金属层。

65. 发明申请

US20070247167A1 Method to monitor critical dimension of IC interconnect 有权
标题翻译：监测IC互连关键尺寸的方法
公开(公告)号：US20070247167A1
公开(公告)日：2007-10-25
申请号：US11398980
申请日：2006-04-06
申请人： Hua Qian , Ching Chung
发明人： Hua Qian , Ching Chung
IPC分类号： G01R31/02
CPC分类号： G01R31/2853
摘要： An example method of monitoring and measuring the line width of interconnects comprising the following steps. First, we measure an I-V profile of a sample interconnect structure to obtain a sample I-V profile. The I-V profile is comprised of leakage current measurements at two or more voltages. The sample interconnect structure is comprised of spaced lines having a line spacing. Next we compare the sample I-V profile with a reference I-V profile at a reference line spacing to determine if sample interconnect structure is not defective. If the sample I-V profile is similar to the reference I-V profile, then leakage currents for the sample interconnect structure are derived from the I-V profiles at a selected voltages. Then we calculate the line spacing of the sample interconnect structure using the sample I-V profile.
摘要翻译：监视和测量互连线宽的示例方法，包括以下步骤。首先，我们测量样品互连结构的I-V轮廓以获得样品I-V轮廓。 I-V曲线由两个或多个电压下的漏电流测量组成。样品互连结构由具有线间隔的间隔线组成。接下来，我们将样本I-V剖面与参考线间距的参考I-V剖面进行比较，以确定样本互连结构是否没有缺陷。如果样品I-V剖面图与参考I-V剖面相似，则样品互连结构的漏电流在选定电压下从I-V剖面得出。然后我们使用样品I-V曲线计算样品互连结构的线间距。

66. 发明申请

US20070244592A1 MANUFACTURING SYSTEM WITH ACTIVE FAILOVER 审中-公开
标题翻译：具有主动故障的制造系统
公开(公告)号：US20070244592A1
公开(公告)日：2007-10-18
申请号：US11736255
申请日：2007-04-17
申请人： Mohd Azizi Chik , Tin Tin Ung , Thangappan Krisnamuthi , Kian Wee Lim , Lip Hong Lim , Brandon Lee
发明人： Mohd Azizi Chik , Tin Tin Ung , Thangappan Krisnamuthi , Kian Wee Lim , Lip Hong Lim , Brandon Lee
IPC分类号： G06F19/00
CPC分类号： G05B19/41865 , G05B2219/31372 , G05B2219/32055 , G05B2219/32269 , G05B2219/45031 , Y02P90/10 , Y02P90/12 , Y02P90/14 , Y02P90/18 , Y02P90/20
摘要： A manufacturing system includes an event trigger to a primary server and a schedule server, forming a control job by the primary server and the schedule server, checks status (such as an end value trigger) of the primary server with a delay by the schedule server, and validating the status of the primary server with a validation process before the schedule server transmits the control job.
摘要翻译：制造系统包括对主服务器和调度服务器的事件触发器，由主服务器和调度服务器形成控制作业，由调度服务器延迟检查主服务器的状态（例如终端值触发器），并在调度服务器发送控制作业之前通过验证过程验证主服务器的状态。

67. 发明授权

US07276797B2 Structure and method for fabricating a bond pad structure 有权
标题翻译：用于制造接合焊盘结构的结构和方法
公开(公告)号：US07276797B2
公开(公告)日：2007-10-02
申请号：US11284981
申请日：2005-11-21
申请人： Zhang Fan , Zhang Bei Chao , Liu Wuping , Chok Kho Liep , Hsia Liang Choo , Lim Yeow Kheng , Alan Cuthbertson , Tan Juan Boon
发明人： Zhang Fan , Zhang Bei Chao , Liu Wuping , Chok Kho Liep , Hsia Liang Choo , Lim Yeow Kheng , Alan Cuthbertson , Tan Juan Boon
IPC分类号： H01L29/40
CPC分类号： H01L24/06 , H01L23/53223 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05559 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2224/05552
摘要： A structure and method for an improved a bond pad structure. A top wiring layer and a top dielectric (IMD) layer over a semiconductor structure are provided. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. A buffer opening is formed in the buffer dielectric layer exposing at least of portion of the top wiring layer. A barrier layer is formed over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. The conductive buffer layer is planarized to form a buffer pad in the buffer opening. A passivation layer is formed over the buffer pad and the buffer dielectric layer. A bond pad opening is formed in the passivation layer over at least a portion of the buffer pad. A bond pad support layer is formed over the buffer pad and the buffer dielectric layer. A bond pad layer is formed over the bond pad support layer. The bond pad layer and the bond pad support layer are patterned to form a bond pad and bond pad support.
摘要翻译：一种改进接合焊盘结构的结构和方法。提供半导体结构上的顶部布线层和顶部电介质（IMD）层。缓冲电介质层形成在顶部布线层和顶部电介质（IMD）层上。在缓冲电介质层中形成缓冲开口，露出至少部分顶部布线层。在缓冲介质层上形成阻挡层，缓冲开口中形成顶部布线层。导电缓冲层形成在阻挡层上。导电缓冲层被平坦化以在缓冲开口中形成缓冲垫。在缓冲垫和缓冲电介质层之上形成钝化层。在缓冲垫的至少一部分上的钝化层中形成接合焊盘开口。在缓冲垫和缓冲电介质层上形成接合焊盘支撑层。接合焊盘层形成在接合焊盘支撑层上。将接合焊盘层和接合焊盘支撑层图案化以形成接合焊盘和接合焊盘支撑。

68. 发明授权

US07259072B2 Shallow low energy ion implantation into pad oxide for improving threshold voltage stability 有权
标题翻译：浅层低能离子注入衬垫氧化物，以提高阈值电压稳定性
公开(公告)号：US07259072B2
公开(公告)日：2007-08-21
申请号：US10828887
申请日：2004-04-21
申请人： Yisuo Li , Francis Benistant , Kim Hyun Sik , Zhao Lun
发明人： Yisuo Li , Francis Benistant , Kim Hyun Sik , Zhao Lun
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L21/823807 , H01L21/823892 , H01L29/78
摘要： A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ species are then implanted using low energy ions of approximately 5 keV into the pad oxide. Conventional As+ or P+ implant follows the shallow implant to form the n-wells. With this procedure of forming a sacrificial shallow implantation oxide layer, surface dopant concentration variation at pad oxide:silicon substrate interface is minimized; and threshold voltage stability variation of the device is significantly decreased.
摘要翻译：描述了一种制造具有增加的阈值电压稳定性的MOSFET器件的方法。在衬底氧化物和衬垫氮化物沉积在硅衬底上并且浅沟槽被图案化并且去除衬垫氮化物之后。然后使用约5keV的低能离子注入到垫氧化物中，将 + /或P + + / 常规作为 +或/或P / N>植入物沿着浅植入物形成n孔。通过形成牺牲浅注入氧化物层的方法，使衬底氧化物：硅衬底界面处的表面掺杂剂浓度变化最小化; 并且器件的阈值电压稳定性变化显着降低。

69. 发明授权

US07253483B2 Semiconductor device layout and channeling implant process 有权
标题翻译：半导体器件布局和沟道植入过程
公开(公告)号：US07253483B2
公开(公告)日：2007-08-07
申请号：US11167640
申请日：2005-06-27
申请人： Yisuo Li , Xiaohong Jiang , Francis Benistant
发明人： Yisuo Li , Xiaohong Jiang , Francis Benistant
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/045
摘要： A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction ) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
摘要翻译：一种使用植入过程形成分级结的装置结构和方法。本发明的实施例包括将离子注入到所述硅衬底中以形成与所述栅极相邻的掺杂区域。 Si晶体结构中的沟道区域（沟道方向<100>）与大角度倾斜和扭曲注入工艺相结合的方向产生具有更梯度结的掺杂区域。取向和植入过程产生更多的离子通道。离子的通道产生更分级的结。当在HV MOS TX上实现时，LDD的分级结增加了击穿电压。另一实施例是具有环形通道区域的FET。

70. 发明申请

US20070173016A1 INTEGRATED CIRCUIT SYSTEM WITH DUMMY REGION 有权
标题翻译：集成电路系统与DUMMY区域
公开(公告)号：US20070173016A1
公开(公告)日：2007-07-26
申请号：US11307142
申请日：2006-01-25
申请人： Dong Sheng Liu , Cing Gie Lim , Subbiah Chettiar Mahadevan , Feng Chen
发明人： Dong Sheng Liu , Cing Gie Lim , Subbiah Chettiar Mahadevan , Feng Chen
IPC分类号： H01L21/8242
CPC分类号： H01L21/7684 , H01L21/3212 , Y10S438/926
摘要： An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first region and the third region is formed between the first region and the second region. An opening is formed in the third region and a material is deposited within the opening for preventing erosion of the first region.
摘要翻译：一种集成电路系统，包括在衬底之内的电介质内形成第一区域，第二区域和第三区域。第一个区域包括钨丝塞。第二区域形成在第一区域的周边的至少一部分附近，第三区域形成在第一区域和第二区域之间。在第三区域中形成开口，并且在开口内沉积材料以防止第一区域的侵蚀。

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