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61. 发明授权

US09202790B2 Semiconductor device for ESD protection 有权
标题翻译：用于ESD保护的半导体器件
公开(公告)号：US09202790B2
公开(公告)日：2015-12-01
申请号：US14411550
申请日：2012-10-22
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Zhongyu Lin , Meng Dai , Yonghai Hu
IPC分类号： H01L27/00 , H01L23/60 , H01L27/02 , H01L29/74 , H01L29/06
CPC分类号： H01L23/60 , H01L27/0262 , H01L29/0692 , H01L29/7436 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device for electrostatic discharge protection includes a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The first, second, third, and fourth heavily-doped regions have the first, second, second, and first conductivity types, respectively. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface.
摘要翻译：用于静电放电保护的半导体器件包括衬底，形成在衬底中的第一阱和第二阱。第一和第二阱分别并列形成，在界面处相遇，分别具有第一导电型和第二导电型。在第一阱中形成第一重掺杂区和第二重掺杂区。在第二阱中形成第三重掺杂区和第四重掺杂区。第一，第二，第三和第四重掺杂区域分别具有第一，第二，第二和第一导电类型。第一和第二重掺杂区域的位置沿平行于界面的方向错开。

62. 发明申请

US20150155182A1 METHOD FOR REMOVING A POLYSILICON PROTECTION LAYER ON A BACK FACE OF AN IGBT HAVING A FIELD STOP STRUCTURE 有权
标题翻译：在具有现场停止结构的IGBT的背面上移除多晶硅保护层的方法
公开(公告)号：US20150155182A1
公开(公告)日：2015-06-04
申请号：US14411978
申请日：2013-07-25
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Qiang Rui , Shuo Zhang , Genyi Wang , Xiaoshe Deng
IPC分类号： H01L21/311 , H01L29/66
CPC分类号： H01L21/31116 , H01L21/32105 , H01L21/32137 , H01L29/66325 , H01L29/66333
摘要： Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.
摘要翻译：公开了一种在具有场停止结构（10）的IGBT的背面上去除多晶硅保护层（12）的方法。该方法包括在IGBT的背面上热氧化多晶硅保护层（12），直到在位于多晶硅保护层（12）上方的栅极氧化物层（11）上终止氧化以形成二氧化硅层（13），并通过干式蚀刻工艺除去形成的二氧化硅层（13）和栅极氧化物层（11）。去除保护层的方法更容易控制。

63. 发明授权

US08890259B2 SCR apparatus and method for adjusting the sustaining voltage 有权
标题翻译： SCR装置和调整维持电压的方法
公开(公告)号：US08890259B2
公开(公告)日：2014-11-18
申请号：US13807317
申请日：2011-12-05
申请人： Meng Dai , Zhongyu Lin
发明人： Meng Dai , Zhongyu Lin
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/74 , H01L31/111 , H01L21/8238 , H01L27/06 , H01L27/02 , H01L29/87 , H01L29/749 , H01L29/10
CPC分类号： H01L27/0623 , H01L27/0262 , H01L29/1016 , H01L29/749 , H01L29/87
摘要： An SCR apparatus includes an SCR structure and a first N injection region. The SCR structure includes a P+ injection region, a P well, an N well and a first N+ injection region, the first N injection region is located under an anode terminal of the P+ injection region of the SCR structure. A method for adjusting a sustaining voltage therefor is provided as well.
摘要翻译： SCR装置包括SCR结构和第一N注入区域。 SCR结构包括P +注入区，P阱，N阱和第一N +注入区，第一N注入区位于SCR结构的P +注入区的阳极端子的下方。还提供了一种用于调整其维持电压的方法。

64. 发明授权

US08884603B2 Reference power supply circuit 有权
标题翻译：参考电源电路
公开(公告)号：US08884603B2
公开(公告)日：2014-11-11
申请号：US13807310
申请日：2011-11-29
申请人： Liang Cheng
发明人： Liang Cheng
IPC分类号： G05F3/20 , G05F3/02 , G05F3/30
CPC分类号： G05F3/02 , G05F3/30
摘要： A reference power supply circuit includes an adjustable resistance network and a bandgap reference power supply circuit, in which the adjustable resistance network includes a first resistor end and a second resistor end, the resistance between the first resistor end and the second resistor end varies with a process deviation; the bandgap reference power supply circuit connects the first resistor end with the second resistor end, for generating a positive proportional to absolute temperature current flowing through the first resistor end and the second resistor end and for outputting a reference voltage related to the positive proportional to absolute temperature current. The reference power supply circuit has the advantageous of high precision and good temperature drift characteristic.
摘要翻译：参考电源电路包括可调电阻网络和带隙参考电源电路，其中可调电阻网络包括第一电阻器端和第二电阻器端，第一电阻器端和第二电阻器端之间的电阻随着过程偏差; 带隙参考电源电路将第一电阻器端与第二电阻器端连接，用于产生与流过第一电阻器端和第二电阻器端的绝对温度电流成比例的正比，并输出与正数成正比的绝对值温度电流。参考电源电路具有精度高，温漂特性好的优点。

65. 发明申请

US20140231893A1 CAPACITOR AND PREPARATION METHOD THEREOF 有权
标题翻译：电容器及其制备方法
公开(公告)号：US20140231893A1
公开(公告)日：2014-08-21
申请号：US14130439
申请日：2012-08-02
申请人： Rengang Qin , Dejin Wang , Boyong He
发明人： Rengang Qin , Dejin Wang , Boyong He
IPC分类号： H01L49/02
CPC分类号： H01L28/75 , C23C16/345 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L28/40
摘要： A capacitor and a method of fabricating thereof are provided. A structure of low pressure tetraethyl orthosilicate-low pressure silicon nitride-low pressure tetraethyl orthosilicate is used in the capacitor to replace the oxide-nitride-oxide structure of the existing capacitor; the capacitor has a relatively high unit capacitance value. Furthermore, the structure of low pressure tetraethyl orthosilicate—low pressure silicon nitride—low pressure tetraethyl orthosilicate is fabricaited by low pressure chemical vapor deposition method at relatively low temperature; thus the heat produced in the whole process is relatively low, which is insufficient to make the semiconductor device shift or make the gate metal layer or the metallized silicon layer peel off. Accordingly, the capacitor and the method of fabricating the capacitor of the present invention can be well applied in the process of the 0.5 μm PIP capacitor or below 0.5 μm.
摘要翻译：提供电容器及其制造方法。在电容器中使用低压四乙基原硅酸盐低压氮化硅 - 低压四乙基原硅酸盐的结构来代替现有电容器的氧化物 - 氮化物 - 氧化物结构; 电容器具有相对高的单位电容值。此外，低压四乙基原硅酸盐低压氮化硅 - 低压四乙基原硅酸盐的结构是通过低温化学气相沉积法在较低的温度下制得的; 因此在整个过程中产生的热量相对较低，这不足以使半导体器件移位或使栅极金属层或金属化硅层剥离。因此，本发明的电容器和制造电容器的方法可以很好地应用于0.5μmPIP电容器或0.5μm以下的工艺。

66. 发明申请

US20130099755A1 LITHIUM BATTERY PROTECTION CIRCUITRY 有权
标题翻译：锂电池保护电路
公开(公告)号：US20130099755A1
公开(公告)日：2013-04-25
申请号：US13807635
申请日：2011-11-29
申请人： Shunhui Lei
发明人： Shunhui Lei
IPC分类号： H02H7/18 , H02J7/00
CPC分类号： H02H7/18 , H02J7/0029 , H02J7/0031 , H02J2007/0039 , Y02E60/12
摘要： A lithium battery protection circuit coupled to a lithium battery is provided. The lithium battery protection circuit includes an over-charge protection circuit and a logic circuit coupled to over-charge protection circuit. The logic circuit has a first logic output and a second logic output. The lithium battery protection circuit also includes a level shift circuit coupled to the logic circuit through the first logic output and the second logic output, and the level shift circuit is configured to convert the first logic output and the second logic output to high voltage levels in an over-charge protection state. Further, the lithium battery protection circuit includes a substrate switching circuit coupled to the level shift circuit and a power transistor coupled between a negative end of the lithium battery and an external circuit negative electrode. The level shift circuit includes a first inverter coupled to the second logic output, a plurality of PMOS transistors, at least one of which has high source-drain voltage and low gate-source voltage, and a plurality of NMOS transistors, at least one of which is a low-voltage NMOS transistor.
摘要翻译：提供耦合到锂电池的锂电池保护电路。锂电池保护电路包括过充电保护电路和耦合到过充电保护电路的逻辑电路。逻辑电路具有第一逻辑输出和第二逻辑输出。锂电池保护电路还包括通过第一逻辑输出和第二逻辑输出耦合到逻辑电路的电平移位电路，并且电平移位电路被配置为将第一逻辑输出和第二逻辑输出转换成高电压电平过充保护状态。此外，锂电池保护电路包括耦合到电平移位电路的衬底切换电路和耦合在锂电池的负端和外部电路负极之间的功率晶体管。电平移位电路包括耦合到第二逻辑输出的第一反相器，多个PMOS晶体管，其中至少一个具有高源极 - 漏极电压和低栅极 - 源极电压，以及多个NMOS晶体管，至少一个其是低电压NMOS晶体管。

67. 发明授权

US10276430B2 Silicon-on-insulator device and intermetallic dielectric layer structure thereof and manufacturing method 有权
公开(公告)号：US10276430B2
公开(公告)日：2019-04-30
申请号：US15119289
申请日：2015-04-29
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Zhiyong Wang , Dejin Wang , Jingjing Ma
IPC分类号： H01L27/12 , H01L23/528 , H01L23/532 , H01L21/768 , H01L21/02
摘要： Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer (54) is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device.

68. 发明授权

US10096699B2 Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US10096699B2
公开(公告)日：2018-10-09
申请号：US14392251
申请日：2014-06-05
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuo Zhang , Qiang Rui , Genyi Wang , Xiaoshe Deng
IPC分类号： H01L29/73 , H01L21/02 , H01L29/739 , H01L29/66 , H01L29/06 , H01L29/08 , H01L21/265 , H01L21/28 , H01L21/285 , H01L21/311 , H01L21/324 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49
摘要： A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).

69. 发明授权

US10084073B2 Lateral insulated-gate bipolar transistor and manufacturing method therefor 有权
公开(公告)号：US10084073B2
公开(公告)日：2018-09-25
申请号：US15537753
申请日：2015-09-28
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shukun Qi
IPC分类号： H01L21/00 , H01L29/00 , H01L29/739 , H01L29/423 , H01L21/265 , H01L29/66 , H01L21/225 , H01L21/3065 , H01L21/02 , H01L21/762 , H01L21/324
CPC分类号： H01L29/7394 , H01L21/02236 , H01L21/2253 , H01L21/26513 , H01L21/3065 , H01L21/324 , H01L21/7624 , H01L29/0623 , H01L29/0834 , H01L29/407 , H01L29/4236 , H01L29/42364 , H01L29/66325
摘要： Provided is a lateral insulated-gate bipolar transistor (LIGBT), comprising a substrate (10), an anode terminal and a cathode terminal on the substrate (10), and a drift region (30) and a gate (61) located between the anode terminal and the cathode terminal. The anode terminal comprises a P-type buried layer (52) on the substrate (10), an N-type buffer region (54) on the P-type buried layer (52), and a P+ collector region (56) on the surface of the N-type buffer region (54). The LIGBT further comprises a trench gate adjacent to the anode terminal, wherein the trench gate penetrates from the surfaces of the N-type buffer region (54) and the P+ collector region (56) to the P-type buried layer (52), and the trench gate comprises an oxidation layer (51) on the inner surface of a trench and polysilicon (53) filled into the oxidation layer.

70. 发明授权

US10056867B2 Sensor control circuit and electronic apparatus 有权
公开(公告)号：US10056867B2
公开(公告)日：2018-08-21
申请号：US15022674
申请日：2014-12-01
申请人： CSMC TECHONLOGIES FAB1 CO., LTD.
发明人： Xueyan Wang , Weiyan Zhang
IPC分类号： H03F3/00 , H03F3/387 , H03F3/45 , H03H7/075 , G01P15/08 , G01P15/12 , H03G1/00
CPC分类号： H03F3/005 , G01P15/0802 , G01P15/123 , H03F3/387 , H03F3/45475 , H03F2200/165 , H03F2200/261 , H03F2200/264 , H03F2203/45138 , H03F2203/45514 , H03G1/0094 , H03H7/075
摘要： A sensor control circuit comprises a sensor (201), a filtering circuit (202), a buffering circuit (203), and an amplifying circuit (204). An output end of the sensor (201) is connected to an input end of the filtering circuit (202), an output end of the filtering circuit (202) is connected to an input end of the buffering circuit (203), and an output end of the buffering circuit (203) is connected to an input end of the amplifying circuit (204). Because the buffering circuit (203) is disposed between the filtering circuit (202) and the amplifying circuit (204), the sensor circuit has an advantage of full sampling. Further provided is an electronic apparatus using the sensor control circuit.

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