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61. 发明授权

US07948024B2 Multi-layered, vertically stacked non-volatile memory device and method of fabrication 有权
标题翻译：多层垂直堆叠的非易失性存储器件和制造方法
公开(公告)号：US07948024B2
公开(公告)日：2011-05-24
申请号：US12484339
申请日：2009-06-15
申请人： Suk-pil Kim , Yoon-dong Park , June-mo Koo , Tae-eung Yoon
发明人： Suk-pil Kim , Yoon-dong Park , June-mo Koo , Tae-eung Yoon
IPC分类号： H01L21/336
CPC分类号： H01L27/11556 , H01L27/11521 , H01L27/11551 , H01L27/11578
摘要： A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.
摘要翻译：提供了一种非易失性存储装置，包括：沿第一方向延伸的第一半导体层，与第一半导体层平行延伸并与第一半导体层分离的第二半导体层，在第一半导体层和第二半导体层之间的隔离层，第一半导体层与第一半导体层之间的第一半导体层，所述隔离层，所述第二半导体层和所述隔离层之间的第二控制栅极电极，其中所述第二控制栅极电极和所述第一控制栅电极分别设置在所述隔离层的相对侧，所述第一控制栅极之间的第一电荷存储层栅电极和第一半导体层，以及在第二控制栅电极和第二半导体层之间的第二电荷存储层。

62. 发明授权

US08299520B2 Semiconductor devices including auxiliary gate electrodes and methods of fabricating the same 有权
标题翻译：包括辅助栅电极的半导体器件及其制造方法
公开(公告)号：US08299520B2
公开(公告)日：2012-10-30
申请号：US12544631
申请日：2009-08-20
申请人： Suk-pil Kim , Yoon-dong Park , Jae-young Choi , June-mo Koo , Byung-hee Hong
发明人： Suk-pil Kim , Yoon-dong Park , Jae-young Choi , June-mo Koo , Byung-hee Hong
IPC分类号： H01L29/66 , H01L29/788 , G11C16/04
CPC分类号： H01L29/66833 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11568 , H01L27/12 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
摘要翻译：根据一些实施例，半导体器件包括第一和第二辅助栅电极以及与第一和第二辅助栅电极交叉的半导体层。主栅电极设置在半导体层上，使得半导体层位于主栅电极和第一和第二辅助栅电极之间。此外，第一和第二辅助栅电极被配置为在半导体层中诱发相应的第一和第二场效应源极/漏极区。还讨论了相关方法。

63. 发明申请

US20090261314A1 Non-volatile memory device and method of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090261314A1
公开(公告)日：2009-10-22
申请号：US12232745
申请日：2008-09-23
申请人： Suk-pil Kim , Yoon-dong Park , June-mo Koo
发明人： Suk-pil Kim , Yoon-dong Park , June-mo Koo
IPC分类号： H01L45/00
CPC分类号： H01L27/249 , H01L27/2409 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146
摘要： Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.
摘要翻译：提供了可以被配置为堆叠结构并且可以更容易地高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。提供至少一个第一电极和至少一个第二电极。所述至少一个第二电极可以穿过所述至少一个第一电极。至少一个数据存储层可以在至少一个第一电极和至少一个第二电极之间的交叉点处。所述至少一个第一电极和所述至少一个第二电极中的任何一个可以包括连接到所述至少一个数据存储层的至少一个结二极管。

64. 发明申请

US20080242011A1 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080242011A1
公开(公告)日：2008-10-02
申请号：US11978567
申请日：2007-10-30
申请人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
发明人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.
摘要翻译：根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。多个下电荷存储层可以形成在半导体层的底表面上。可以在多个下电荷存储层上形成多个下控制栅电极。多个上电荷存储层可以形成在半导体层的顶表面上。多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

65. 发明授权

US08379480B2 Non-volatile memory device and method of manufacturing the same 有权
公开(公告)号：US08379480B2
公开(公告)日：2013-02-19
申请号：US13370856
申请日：2012-02-10
申请人： Kwang-soo Seol , Yoon-dong Park , Suk-pil Kim
发明人： Kwang-soo Seol , Yoon-dong Park , Suk-pil Kim
IPC分类号： G11C8/00
CPC分类号： H01L29/7926 , G11C16/0483 , G11C16/10 , H01L27/0688 , H01L27/11517 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/792
摘要： A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.

66. 发明授权

US08159017B2 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08159017B2
公开(公告)日：2012-04-17
申请号：US12385201
申请日：2009-04-01
申请人： Kwang-soo Seol , Yoon-dong Park , Suk-pil Kim
发明人： Kwang-soo Seol , Yoon-dong Park , Suk-pil Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/7926 , G11C16/0483 , G11C16/10 , H01L27/0688 , H01L27/11517 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/792
摘要： A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.
摘要翻译：一种多层非易失性存储器件及其制造方法。非易失性存储器件可以包括具有堆叠结构的多个第一半导体层。多个控制栅电极可以跨越第一半导体层延伸。第一体接触层可以跨越第一半导体层延伸。可以在控制栅电极和第一半导体层之间插入多个电荷存储层。

67. 发明申请

US20100067301A1 COLUMNAR NON-VOLATILE MEMORY DEVICES WITH AUXILIARY TRANSISTORS AND METHODS OF OPERATING THE SAME 有权
标题翻译：具有辅助晶体管的柱状非易失性存储器件及其操作方法
公开(公告)号：US20100067301A1
公开(公告)日：2010-03-18
申请号：US12493935
申请日：2009-06-29
申请人： Suk-pil Kim , Yoon-dong Park
发明人： Suk-pil Kim , Yoon-dong Park
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L21/28273 , G11C16/10 , H01L21/28282 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/792 , H01L29/7926
摘要： A non-volatile memory device includes at least one semiconductor column having a first sidewall and a second sidewall. The device also includes at least one gate electrode is disposed on the first sidewall and at least one control gate electrode disposed on the second sidewall. The device further includes at least one charge storage layer is disposed between the second sidewall and the at least one control gate electrode. The at least one gate electrode and the at least one control gate electrode may be disposed on opposite sides of the at least one semiconductor column such that they commonly control a channel region in the semiconductor column.
摘要翻译：非易失性存储器件包括至少一个具有第一侧壁和第二侧壁的半导体柱。该器件还包括设置在第一侧壁上的至少一个栅电极和设置在第二侧壁上的至少一个控制栅电极。该装置还包括至少一个电荷存储层设置在第二侧壁和至少一个控制栅电极之间。至少一个栅电极和至少一个控制栅电极可以设置在至少一个半导体柱的相对侧上，使得它们共同地控制半导体柱中的沟道区。

68. 发明申请

US20100065899A1 SEMICONDUCTOR DEVICES INCLUDING AUXILIARY GATE ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：包括辅助电极的半导体器件及其制造方法
公开(公告)号：US20100065899A1
公开(公告)日：2010-03-18
申请号：US12544631
申请日：2009-08-20
申请人： Suk-pil Kim , Yoon-dong Park , Jae-young Choi , June-mo Koo , Byung-hee Hong
发明人： Suk-pil Kim , Yoon-dong Park , Jae-young Choi , June-mo Koo , Byung-hee Hong
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/66833 , B82Y10/00 , G11C16/0483 , H01L27/11521 , H01L27/11568 , H01L27/12 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A semiconductor device may include first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode may be provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes may be configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
摘要翻译：半导体器件可以包括第一和第二辅助栅极电极以及与第一和第二辅助栅电极交叉的半导体层。主栅电极可以设置在半导体层上，使得半导体层位于主栅极和第一和第二辅助栅电极之间。此外，第一和第二辅助栅电极可以被配置为在半导体层中诱发相应的第一和第二场效应型源极/漏极区。还讨论了相关方法。

69. 发明申请

US20090251963A1 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090251963A1
公开(公告)日：2009-10-08
申请号：US12385201
申请日：2009-04-01
申请人： Kwang-soo Seol , Yoon-dong Park , Suk-pil Kim
发明人： Kwang-soo Seol , Yoon-dong Park , Suk-pil Kim
IPC分类号： G11C16/04 , H01L29/792 , G11C16/06
CPC分类号： H01L29/7926 , G11C16/0483 , G11C16/10 , H01L27/0688 , H01L27/11517 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/792
摘要： A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.
摘要翻译：一种多层非易失性存储器件及其制造方法。非易失性存储器件可以包括具有堆叠结构的多个第一半导体层。多个控制栅电极可以跨越第一半导体层延伸。第一体接触层可以跨越第一半导体层延伸。可以在控制栅电极和第一半导体层之间插入多个电荷存储层。

70. 发明授权

US08648945B2 Image sensors for sensing object distance information based on clock signals 有权
标题翻译：用于基于时钟信号感测物体距离信息的图像传感器
公开(公告)号：US08648945B2
公开(公告)日：2014-02-11
申请号：US12954835
申请日：2010-11-26
申请人： Ilia Ovsiannikov , Yoon-dong Park , Dong-ki Min , Young-gu Jin
发明人： Ilia Ovsiannikov , Yoon-dong Park , Dong-ki Min , Young-gu Jin
IPC分类号： H04N3/14 , H04N5/335 , H04N7/18 , G01C3/08
CPC分类号： G01B11/026 , G01S7/4912 , G01S7/4914 , G01S17/023 , G01S17/89
摘要： An image sensor includes a clock signal generator configured to generate and output at least first and second clock signals, a plurality of pixels configured to generate associated distance signals based on corresponding clock signals from among the at least first and second clock signals and light reflected by an object, and a distance information deciding unit configured to determine distance information with respect to the object by using the associated distance signals. At least one first pixel from among the plurality of pixels is configured to generate the associated distance signal based on at least the first clock signal, and at least one second pixel from among the plurality of pixels, which is adjacent to the at least one first pixel, is configured to generate the associated distance signal based on at least the second clock signal.
摘要翻译：图像传感器包括：时钟信号发生器，被配置为产生并输出至少第一和第二时钟信号;多个像素，被配置为基于来自所述至少第一和第二时钟信号中的相应时钟信号和由对象和距离信息决定单元，被配置为通过使用相关联的距离信号来确定关于对象的距离信息。所述多个像素中的至少一个第一像素被配置为基于至少所述第一时钟信号和所述多个像素中的至少一个第二像素生成所述相关距离信号，所述至少一个第二像素与所述至少一个第一像素，被配置为基于至少第二时钟信号来生成相关联的距离信号。

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