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61. 发明申请

US20090279367A1 POWER SAVING SENSING SCHEME FOR SOLID STATE MEMORY 有权
标题翻译：用于固态存储器的省电感应方案
公开(公告)号：US20090279367A1
公开(公告)日：2009-11-12
申请号：US12502932
申请日：2009-07-14
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/10 , G11C7/02
CPC分类号： G11C8/12 , G11C7/103 , G11C8/18
摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.
摘要翻译：公开了诸如涉及固态存储器件的方法和装置。一种这样的方法包括选择存储器阵列中的多个存储器单元。确定存储在所选择的多个存储单元中的多个数据位的状态。在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。顺序提供多个数据位作为输出。在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。

62. 发明授权

US07596039B2 Input-output line sense amplifier having adjustable output drive capability 有权
标题翻译：具有可调输出驱动能力的输入输出线路读出放大器
公开(公告)号：US07596039B2
公开(公告)日：2009-09-29
申请号：US11706937
申请日：2007-02-14
申请人： Kang Yong Kim , Chulmin Jung
发明人： Kang Yong Kim , Chulmin Jung
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/1096 , G11C7/00 , G11C7/02 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/4091 , G11C11/4097 , G11C13/004 , H03F3/16
摘要： An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output driver stage having a plurality of different programmable output drive capacities to tailor the output drive of the sense amplifier.
摘要翻译：输入 - 输出线路读出放大器被配置为通过输入 - 输出信号线将输入数据信号驱动到输出驱动器电路，输入 - 输出线路读出放大器具有输出驱动级，其具有多个不同的可编程输出驱动能力，以定制读出放大器的输出驱动。

63. 发明申请

US20090059707A1 POWER SAVING SENSING SCHEME FOR SOLID STATE MEMORY 有权
公开(公告)号：US20090059707A1
公开(公告)日：2009-03-05
申请号：US11847559
申请日：2007-08-30
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C8/12
CPC分类号： G11C8/12 , G11C7/103 , G11C8/18
摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

64. 发明授权

US07433249B2 Apparatus with equalizing voltage generation circuit and methods of use 有权
标题翻译：具有均衡电压产生电路和使用方法的装置
公开(公告)号：US07433249B2
公开(公告)日：2008-10-07
申请号：US11347961
申请日：2006-02-06
申请人： Chulmin Jung
发明人： Chulmin Jung
IPC分类号： G11C5/14
CPC分类号： G11C11/4094
摘要： A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.
摘要翻译：存储器件包括均衡电压发生器。均衡电压发生器包括振荡器和电荷泵以产生第一电压，其可以用作互补数字线对的均衡电压。振荡器由均衡电压发生器的反馈和控制回路产生的振荡器控制信号控制。反馈和控制回路包括参考发生器电路，以产生稳定的内部参考信号，其被钳位在最大参考电压。反馈和控制环路的比较器将内部参考信号与第一电压成比例的第二电压进行比较。当第二电压低于参考电压时，比较器使振荡器导通，并且当第二电压高于参考电压时使振荡器关断。

65. 发明授权

US08183126B2 Patterning embedded control lines for vertically stacked semiconductor elements 有权
标题翻译：为垂直堆叠的半导体元件绘制嵌入式控制线
公开(公告)号：US08183126B2
公开(公告)日：2012-05-22
申请号：US12502178
申请日：2009-07-13
申请人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
发明人： Hyung-Kyu Lee , YoungPil Kim , Peter Nicholas Manos , Maroun Khoury , Dadi Setiadi , Chulmin Jung , Hsing-Kuen Liou , Paramasiyan Kamatchi Subramanian , Yongchul Ahn , Jinyoung Kim , Antoine Khoueir
IPC分类号： H01L21/30
CPC分类号： H01L27/101 , H01L27/228 , H01L27/2454 , H01L27/2463 , H01L43/08 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1675
摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
摘要翻译：本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

66. 发明申请

US20110299323A1 Floating Source Line Architecture for Non-Volatile Memory 有权
标题翻译：非易失性存储器的浮动源线架构
公开(公告)号：US20110299323A1
公开(公告)日：2011-12-08
申请号：US13206550
申请日：2011-08-10
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0002 , G11C7/12 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0069
摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
摘要翻译：一种用于将数据写入诸如RRAM存储器单元的非易失性存储单元的方法和装置。在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。源极线连接到开关器件，并将一系列存储器单元连接在一起。此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并通过至少一部分剩余的RSE连接到所选择的源线。

67. 发明授权

US07974117B2 Non-volatile memory cell with programmable unipolar switching element 有权
标题翻译：具有可编程单极开关元件的非易失性存储单元
公开(公告)号：US07974117B2
公开(公告)日：2011-07-05
申请号：US12497964
申请日：2009-07-06
申请人： Wei Tan , Nurul Amin , Insik Jim , Ming Sun , Venu Vaithyanathan , YoungPil Kim , Chulmin Jung
发明人： Wei Tan , Nurul Amin , Insik Jim , Ming Sun , Venu Vaithyanathan , YoungPil Kim , Chulmin Jung
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/56 , G11C2213/76
摘要： A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.
摘要翻译：公开了一种具有可编程单极开关元件的非易失性存储单元，以及编程存储器元件的方法。在一些实施例中，存储单元包括与可编程单极性电阻感测开关元件串联连接的可编程双极性电阻读出存储元件。通过在所选择的方向上通过单元施加选择的写入电流将存储元件编程为所选择的电阻状态，其中通过沿第一方向的写入电流来编程第一电阻电平，并且其中第二电阻电平被编程通过在相反的第二方向上的写入电流。开关元件被编程为所选择的电阻水平以便于访问存储元件的所选择的电阻状态。

68. 发明申请

US20110007547A1 Vertical Non-Volatile Switch with Punchthrough Access and Method of Fabrication Therefor 有权
公开(公告)号：US20110007547A1
公开(公告)日：2011-01-13
申请号：US12502089
申请日：2009-07-13
申请人： Maroun Georges Khoury , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , YoungPil Kim
发明人： Maroun Georges Khoury , Hyung-Kyu Lee , Peter Nicholas Manos , Chulmin Jung , YoungPil Kim
IPC分类号： G11C11/40 , H01L29/66
CPC分类号： H01L27/101 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C2213/79 , H01L29/8618
摘要： A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.

69. 发明申请

US20100177577A1 SIGNAL TRANSFER APPARATUS AND METHODS 有权
标题翻译：信号传输装置和方法
公开(公告)号：US20100177577A1
公开(公告)日：2010-07-15
申请号：US12730994
申请日：2010-03-24
申请人： Chulmin Jung , Kang Yong Kim
发明人： Chulmin Jung , Kang Yong Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/103 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括被配置为接收多个信号的多个节点。信号可以表示存储在诸如存储器装置的装置的多个存储单元中的信息。该设备可以包括多个传输路径，其具有耦合在节点和输出节点之间的存储元件。传输路径可以被配置为经由传输路径之一将信号的选定信号从节点之一传送到输出节点。传送路径可以被配置为仅将所选信号的值保存在仅一个存储元件中。每个传送路径可以仅包括一个存储元件。公开了包括附加装置，系统和方法的其它实施例。

70. 发明授权

US07212460B1 Line amplifier to supplement line driver in an integrated circuit 有权
标题翻译：线路放大器，用于补充集成电路中的线路驱动器
公开(公告)号：US07212460B1
公开(公告)日：2007-05-01
申请号：US11294729
申请日：2005-12-05
申请人： Chulmin Jung , George Raad
发明人： Chulmin Jung , George Raad
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/08 , G11C11/4074 , G11C11/4091 , G11C2207/065
摘要： A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line amplifier positioned at a distance from the circuitry that drives signals onto the line, for example, across a memory array. The line amplifier detects the driven signal on the line at early stages, and even before the signal reaches its full potential, the amplifier amplifies that signal and drives it back to the line to help boost the detected signal. In a preferred embodiment, the amplifier comprises a differential amplifier capable of boosting one of two input signal lines. In an alternative embodiment, the amplifier output may additionally input to a feedback loop, which loop ultimately drives a pull-up transistor to boost the detected signal and passes it back to the line to even further assist the differential amplifier in boosting. Use of the disclosed circuitry benefits, as one example, the boosting of a DRAM column select line that passes a long distance through the memory array.
摘要翻译：公开了一种用于沿着电路线升高驱动信号以减少RC延迟的方法和电路。在一个实施例中，该电路包括一个线路放大器，该线路放大器定位在与电路相距一定距离处，例如跨越存储器阵列驱动信号到线路上。线路放大器在早期阶段检测线路上的驱动信号，甚至在信号达到其全部电位之前，放大器放大该信号并将其驱动回线路，以帮助提高检测到的信号。在优选实施例中，放大器包括能够升压两个输入信号线之一的差分放大器。在替代实施例中，放大器输出可以另外输入到反馈回路，该回路最终驱动上拉晶体管以升高检测到的信号并将其返回到线以进一步辅助差分放大器的升压。作为一个示例，使用所公开的电路有利于升高通过存储器阵列的长距离的DRAM列选择线。

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