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61. 发明授权

US07268042B2 Nonvolatile semiconductor memory and making method thereof 有权
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US07268042B2
公开(公告)日：2007-09-11
申请号：US11005015
申请日：2004-12-07
申请人： Digh Hisamoto , Kan Yasui
发明人： Digh Hisamoto , Kan Yasui
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11531 , H01L29/66825
摘要： A nonvolatile semiconductor memory device of a split gate structure having a gate of low resistance suitable to the arrangement of a memory cell array is provided. When being formed of a side wall spacer, a memory gate is formed of polycrystal silicon and then replaced with nickel silicide. Thus, its resistance can be lowered with no effect on the silicidation to the selection gate or the diffusion layer.
摘要翻译：提供了具有适合于存储单元阵列的布置的具有低电阻的栅极的分离栅极结构的非易失性半导体存储器件。当由侧壁间隔物形成时，存储栅由多晶硅形成，然后被硅化镍替代。因此，其电阻可以降低，而对选择栅极或扩散层的硅化物没有影响。

62. 发明申请

US20070207581A1 Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same 有权
公开(公告)号：US20070207581A1
公开(公告)日：2007-09-06
申请号：US11797839
申请日：2007-05-08
申请人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/4232 , H01L29/792
摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

63. 发明授权

US07259422B1 Nonvolatile semiconductor memory device and its fabrication method 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07259422B1
公开(公告)日：2007-08-21
申请号：US11653832
申请日：2007-01-17
申请人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Daisuke Okada
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.
摘要翻译：存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

64. 发明授权

US07245531B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07245531B2
公开(公告)日：2007-07-17
申请号：US11198191
申请日：2005-08-08
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C11/34
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.
摘要翻译：存储单元以多个阵列形式布置。选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。存储器栅极电极分别由存储器栅极线连接。分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔部分。

65. 发明申请

US20070145455A1 Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate 有权
标题翻译：非易失性半导体器件和制造具有侧壁栅极的嵌入式非易失性半导体存储器件的方法
公开(公告)号：US20070145455A1
公开(公告)日：2007-06-28
申请号：US11452256
申请日：2006-06-14
申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-ichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru , Shin-ichiro Kimura
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , G11C16/0425 , H01L27/11568 , H01L29/42344
摘要： A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.
摘要翻译：提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而导致的最佳栅极高度的差异而引入的注入离子的问题，以及一个缩放的MOS晶体管。形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于在逻辑区域的栅电极。栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

66. 发明授权

US07235441B2 Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same 有权
标题翻译：具有锥形侧壁栅极的非易失性半导体存储器件及其制造方法
公开(公告)号：US07235441B2
公开(公告)日：2007-06-26
申请号：US10901347
申请日：2004-07-29
申请人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/4232 , H01L29/792
摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.
摘要翻译：在其中使用电荷存储膜的非易失性存储器的MOS晶体管和用于选择它的MOS晶体管相邻形成的分离栅极型非易失性存储单元中，电荷存储特性得到改善，栅电极的电阻降低。为了防止电荷存储薄膜的拐角部分的厚度减小并且提高电荷存储特性，在选择栅电极的侧壁上形成锥形。此外，为了稳定地进行用于降低自对准栅电极的电阻的硅化物工艺，选择栅电极的侧壁凹陷。或者，在自对准栅电极的上部和选择栅电极的上部之间形成不连续。

67. 发明申请

US20060281262A1 Integrated semiconductor nonvolatile storage device 有权
标题翻译：集成半导体非易失性存储装置
公开(公告)号：US20060281262A1
公开(公告)日：2006-12-14
申请号：US11437610
申请日：2006-05-22
申请人： Digh Hisamoto , Shin'ichiro Kimura , Daiske Okada , Kan Yasui
发明人： Digh Hisamoto , Shin'ichiro Kimura , Daiske Okada , Kan Yasui
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/115 , G11C16/0425 , H01L21/28282 , H01L27/11568 , H01L29/792
摘要： An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.
摘要翻译：本发明的目的是提供一种可以高速读取并重新编程次数增加的集成半导体非易失性存储装置。在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。为了克服这个问题，本发明的集成半导体非易失性存储装置被配置为使得具有不同存储器栅极长度的存储单元集成在同一芯片上。这允许以高速读取设备并重新编程增加的次数。

68. 发明申请

US20060239072A1 Nonvolatile memory device and semiconductor device 有权
标题翻译：非易失性存储器件和半导体器件
公开(公告)号：US20060239072A1
公开(公告)日：2006-10-26
申请号：US11472993
申请日：2006-06-23
申请人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
发明人： Toshihiro Tanaka , Takashi Yamaki , Yutaka Shinagawa , Daisuke Okada , Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/10 , G11C16/0433
摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1 iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1 iA to flow a current in the memory cell.
摘要翻译：这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。并且，在恒定电流源晶体管中流动约1IA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。

69. 发明授权

US07115943B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07115943B2
公开(公告)日：2006-10-03
申请号：US11013406
申请日：2004-12-17
申请人： Toshiyuki Mine , Natsuki Yokoyama , Kan Yasui
发明人： Toshiyuki Mine , Natsuki Yokoyama , Kan Yasui
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/792
摘要： A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.
摘要翻译：分离栅结构的MONOS非易失性存储器，其中由热电子和热孔分别执行写入和擦除容易导致电子不被擦除并且保留在选择栅极电极侧壁上的氮化硅膜中，并且结果在改写耐久性的恶化。当长时间擦除作为解决该问题的措施时，会出现缺点，例如由擦除电流的增加引起的电路面积的增加和保留特性的劣化。在本发明中，通过能够进行取向沉积的反应等离子体溅射沉积方法形成氮化硅膜，并且在形成顶部Si氧化物膜时，在选择栅电极侧壁上除去Si氮化物膜。

70. 发明申请

US20060035435A1 Semiconductor device and manufacturing method for semiconductor device to reduce the lithography masks 有权
标题翻译：用于半导体器件的半导体器件和制造方法来减少光刻掩模
公开(公告)号：US20060035435A1
公开(公告)日：2006-02-16
申请号：US11189078
申请日：2005-07-26
申请人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru
发明人： Kan Yasui , Digh Hisamoto , Tetsuya Ishimaru
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/42344
摘要： Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x
摘要翻译：用于减少在标准CMOS工艺中添加到非易失性存储器中的所需光刻掩模的数量的半导体器件和制造方法，以缩短生产周期并降低成本。在具有利用侧壁结构的硅化栅电极的分裂栅极存储单元中，形成邻接所选择的栅电极的单独的辅助图案。通过填充电极和辅助图案之间的间隙中的多晶硅的侧壁栅极，将接触设置在自对准的布线层上。考虑到占用的表面积的大小，接触可以以最佳设计重叠在辅助图案和设备隔离区域上。如果到选定的栅电极的距离为x，则ONO膜沉积厚度为t，多晶硅膜沉积厚度为d，则辅助图案可以仅分开距离x，使得x <2x（t + d）。

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