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    • 64. 发明授权
    • Specifically crosslinked hemoglobin with free functionality
    • 具有自由功能的具有交联性的血红蛋白
    • US5399671A
    • 1995-03-21
    • US978418
    • 1992-11-18
    • Ronald KlugerYonghong Song
    • Ronald KlugerYonghong Song
    • A61K38/16A61K38/00A61K47/48A61P7/08C07C69/86C07K1/113C07K14/805C07C103/52A61K35/14C07K13/00
    • C07K14/805A61K47/48307C07C69/76A61K38/00
    • Hemoglobin is site-specifically crosslinked into its tetrameric form by reaction with a trifunctional reagent which combines electrostatic effects, steric effects and the presence of functional groups so that two of the functional groups react with specific sites on the hemoglobin whilst the third site is left free for reaction with endogenous nucleophilic compounds. A specific example of such a crosslinking reagent is trimesoyl tris(3,5-dibromosalicylate), TTDS, which effects specific crosslinking between the amino groups of lysine-82 on each respective .beta. sub-unit. While the crosslinking reagent TTDS has three available carboxyl groups for the crosslinking reaction, only two so react, leaving one free carboxyl for reaction with exogenous nucleophiles, e.g. to render the hemoglobin product useful as a carrier for nucleophilic compounds through the body's circulatory system.
    • 血红蛋白通过与三官能试剂反应进行位置特异性交联成四聚体形式,其结合了静电效应,空间效应和功能基团的存在,使得两个官能团与血红蛋白上的特定位点反应,而第三位点保持游离 用于与内源性亲核化合物反应。 这种交联试剂的具体实例是均苯三甲酸三(3,5-二溴水杨酸酯)TTDS,其在每个相应的β子单元上影响赖氨酸-82的氨基之间的特异性交联。 虽然交联剂TTDS具有三个用于交联反应的可用羧基,但仅有两个反应,留下一个游离羧基用于与外源亲核试剂反应,例如, 以使血红蛋白产物通过身体的循环系统用作亲核化合物的载体。
    • 65. 发明授权
    • Minimizing register spills by using register moves
    • 通过使用寄存器移动来最小化寄存器溢出
    • US09009692B2
    • 2015-04-14
    • US12647484
    • 2009-12-26
    • Spiros KalogeropulosPartha P. TirumalaiYonghong Song
    • Spiros KalogeropulosPartha P. TirumalaiYonghong Song
    • G06F9/45
    • G06F8/441
    • A system and method for minimizing register spills during compilation. A compiler reallocates spilled variables from stack memory to other available registers. Although a corresponding register file may not have available registers for storage, the compiler identifies available registers in other locations for storage. The compiler identifies available registers in an alternate register file, wherein the alternate register file may be a floating-point register file which is then used for spilled integer variables. Other instruction type combinations between spilled variables and alternate register files are possible. When an available register within the alternate register file is identified, the compiler modifies the program instructions to allocate the corresponding spilled variable to the available register.
    • 一种用于在编译期间最小化寄存器溢出的系统和方法。 编译器将溢出的变量从堆栈内存重新分配给其他可用的寄存器。 虽然相应的寄存器文件可能没有可用的存储寄存器,但编译器可以识别其他位置的可用寄存器进行存储。 编译器识别备用寄存器文件中的可用寄存器,其中备用寄存器文件可以是浮点寄存器文件,然后用于溢出的整数变量。 溢出变量和备用寄存器文件之间的其他指令类型组合是可能的。 当识别备用寄存器文件中的可用寄存器时,编译器会修改程序指令,将相应的溢出变量分配给可用的寄存器。
    • 66. 发明授权
    • Parallelizing non-countable loops with hardware transactional memory
    • 将不可计数的循环与硬件事务内存并行化
    • US08739141B2
    • 2014-05-27
    • US12123176
    • 2008-05-19
    • Yonghong SongSpiros KalogeropulosPartha P. Tirumalai
    • Yonghong SongSpiros KalogeropulosPartha P. Tirumalai
    • G06F9/45
    • G06F9/3004G06F8/452G06F9/30087G06F9/325G06F9/3863
    • A system and method for speculatively parallelizing non-countable loops in a multi-threaded application. A multi-core processor receives instructions for a multi-threaded application. The application may contain non-countable loops. Non-countable loops have an iteration count value that cannot be determined prior to the execution of the non-countable loop, a loop index value that cannot be non-speculatively determined prior to the execution of an iteration of the non-countable loop, and control that is not transferred out of the loop body by a code line in the loop body. The compiler replaces the non-countable loop with a parallelized loop pattern that uses outlined function calls defined in a parallelization library (PL) in order to speculatively execute iterations of the parallelized loop. The parallelized loop pattern is configured to squash and re-execute any speculative thread of the parallelized loop pattern that is signaled to have a transaction failure.
    • 一种用于在多线程应用程序中推测并行化不可计数循环的系统和方法。 多核处理器接收多线程应用程序的指令。 应用程序可能包含不可计数的循环。 非可计数循环具有在执行非可计数循环之前无法确定的迭代计数值,循环索引值在执行非可数循环的迭代之前不能非推测性地确定,并且 没有通过循环体中的代码行从循环体中传出的控制。 编译器使用并行循环模式来替换非可数循环,该模式使用在并行化库(PL)中定义的概述函数调用,以便推测执行并行化循环的迭代。 并行化循环模式被配置为压缩并重新执行被指示为具有事务失败的并行化循环模式的任何推测线程。
    • 67. 发明授权
    • Static profitability control for speculative automatic parallelization
    • 投机自动并行化的静态盈利能力控制
    • US08677337B2
    • 2014-03-18
    • US12113716
    • 2008-05-01
    • Yonghong SongSpiros KalogeropulosPartha P. Tirumalai
    • Yonghong SongSpiros KalogeropulosPartha P. Tirumalai
    • G06F9/45
    • G06F8/456
    • A compilation method and mechanism for parallelizing program code. A method for compilation includes analyzing source code and identifying candidate code for parallelization. Having identified one or more suitable candidates, the profitability of parallelizing the candidate code is determined. If the profitability determination meets a predetermined criteria, then the candidate code may be parallelized. If, however, the profitability determination does not meet the predetermined criteria, then the candidate code may not be parallelized. Candidate code may comprises a loop, and determining profitability of parallelization may include computing a probability of transaction failure for the loop. Additionally, a determination of an execution time of a parallelized version of the loop is made. If the determined execution time is less than an execution time of a non-parallelized version of said loop by at least a given amount, then the loop may be parallelized. If the determined execution time is not less than an execution time of a non-parallelized version of said loop by at least a given amount, then the loop may not be parallelized.
    • 用于并行化程序代码的编译方法和机制。 一种编译方法包括分析源代码和识别用于并行化的候选代码。 确定了一个或多个合适的候选者后,确定并行化候选代码的盈利能力。 如果盈利能力确定满足预定标准,则候选代码可以并行化。 然而,如果盈利能力确定不符合预定标准,则候选代码可能不并行化。 候选代码可以包括循环,并且确定并行化的获利能力可以包括计算循环的事务失败概率。 此外,进行环路的并行化版本的执行时间的确定。 如果确定的执行时间小于所述循环的非并行化版本的执行时间至少给定量,则可以并行化该循环。 如果确定的执行时间不小于所述循环的非并行化版本的执行时间至少给定量,则循环可能不并行化。
    • 68. 发明授权
    • Value predictable variable scoping for speculative automatic parallelization with transactional memory
    • 值可预测的变量范围,用于事务性内存的投机自动并行化
    • US08239843B2
    • 2012-08-07
    • US12046365
    • 2008-03-11
    • Yonghong SongXiangyun KongSpiros KalogeropulosPartha P. Tirumalai
    • Yonghong SongXiangyun KongSpiros KalogeropulosPartha P. Tirumalai
    • G06F9/45
    • G06F8/456
    • Parallelize a computer program by scoping program variables at compile time and inserting code into the program. Identify as value predictable variables, variables that are: defined only once in a loop of the program; not defined in any inner loop of the loop; and used in the loop. Optionally also: identify a code block in the program that contains a variable assignment, and then traverse a path backwards from the block through a control flow graph of the program. Name in a set all blocks along the path until a loop header block. For each block in the set, determine program blocks that logically succeed the block and are not in the first set. Identify all paths between the block and the determined blocks as failure paths, and insert code into the failure paths. When executed at run time of the program, the inserted code fails the corresponding path.
    • 通过在编译时对程序变量进行范围并将代码插入程序来并行化计算机程序。 识别为值可预测变量,变量是:在程序循环中仅定义一次; 没有在循环的任何内循环中定义; 并在循环中使用。 还可以:识别包含变量赋值的程序中的代码块,然后通过程序的控制流程图从块向后移动一个路径。 命名一个路径中的所有块,直到循环头块。 对于集合中的每个块,确定在块上逻辑成功并且不在第一组中的程序块。 将块和确定的块之间的所有路径标识为故障路径,并将代码插入故障路径。 当在程序的运行时执行时,插入的代码失败相应的路径。
    • 70. 发明申请
    • PIPELINED PARALLELIZATION WITH LOCALIZED SELF-HELPER THREADING
    • 具有本地化自助螺线管的管道并联
    • US20110067014A1
    • 2011-03-17
    • US12559167
    • 2009-09-14
    • Yonghong SongSpiros KalogeropulosPartha P. Tirumalai
    • Yonghong SongSpiros KalogeropulosPartha P. Tirumalai
    • G06F9/45
    • G06F8/456
    • A system and method for automatically parallelizing a computer program for multi-threaded execution. A compiler identifies and parallelizes non-DOALL parallel regions, such as loops, within a computer program. The compiler determines enhanced helper thread instructions based upon the main body instructions of the non-DOALL region. These helper thread instructions are inserted ahead of the main body instructions within each of the plurality of threads, rather than within a single main thread. Next, synchronization instructions are inserted in one or more threads such that the main body of work of each thread is performed in a pipelined manner. The helper thread instructions within each thread may reduce the total execution time of each thread.
    • 一种用于自动并行化计算机程序以进行多线程执行的系统和方法。 编译器在计算机程序内识别和并行非DOALL并行区域,例如循环。 编译器基于非DOALL区域的主体指令来确定增强的助手线程指令。 这些辅助线程指令被插入在多个线程的每一个内的主体指令之前,而不是在单个主线程内。 接下来,将同步指令插入到一个或多个线程中,使得每个线程的主要工作主体以流水线方式执行。 每个线程内的辅助线程指令可能会减少每个线程的总执行时间。