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61. 发明授权

US09113416B2 System and method for reducing overhead of searcher tasks for discontinuous reception 有权
标题翻译：用于减少不连续接收的搜索者任务的开销的系统和方法
公开(公告)号：US09113416B2
公开(公告)日：2015-08-18
申请号：US13290033
申请日：2011-11-04
申请人： Jimmy C. Chui , An-swol C. Hu , Jittra Jootar , Feng Lu , Yi Su
发明人： Jimmy C. Chui , An-swol C. Hu , Jittra Jootar , Feng Lu , Yi Su
IPC分类号： G08C17/00 , H04W52/02 , H04W52/14
CPC分类号： H04W52/0274 , H04W52/02 , H04W52/028 , H04W52/14 , Y02D70/00 , Y02D70/1224 , Y02D70/1242 , Y02D70/1244 , Y02D70/1246 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/164 , Y02D70/24 , Y02D70/25
摘要： At least one feature pertains to a method of communication that comprises aligning a measurement task that utilizes a resource within a user equipment, such that at least a portion of the measurement task is performed during a time that the resource is enabled in the user equipment, and executing the measurement task during the time that the resource is enabled in the user equipment. In one example, the measurement task may be a searcher task, the resource may comprise receiver circuitry, and the time that the resource is enabled corresponds to a DRX monitoring interval of a downlink channel, such as a high speed shared control channel. By aligning and executing the searcher task during the time that the resource is enabled in the user equipment, searcher overhead may be reduced. Reducing searcher overhead allows the user equipment to save power by disabling the receiver circuitry.
摘要翻译：至少一个特征涉及一种通信方法，包括对齐利用用户设备内的资源的测量任务，使得在用户设备中启用资源的时间期间执行测量任务的至少一部分，并在用户设备中启用资源的时间内执行测量任务。在一个示例中，测量任务可以是搜索者任务，资源可以包括接收机电路，并且资源被启用的时间对应于诸如高速共享控制信道的下行链路信道的DRX监视间隔。通过在用户设备中启用资源的时间内对齐和执行搜索者任务，可以减少搜索者开销。减少搜索器开销允许用户设备通过禁用接收器电路来节省电力。

62. 发明授权

US08812299B1 Class-based language model and use 有权
标题翻译：基于类的语言模型和使用
公开(公告)号：US08812299B1
公开(公告)日：2014-08-19
申请号：US12943426
申请日：2010-11-10
申请人： Yi Su
发明人： Yi Su
IPC分类号： G06F17/27
CPC分类号： G06F17/2818 , G06F17/2715 , G06F17/2785
摘要： This disclosure describes novel generation and use of a class-based language model. For example, one embodiment herein includes detecting presence of a common word that is used in different contexts in a word pool and assigning the common word to each of multiple classes in a class-based language model. Generation of the class-based language model and assignment of the common word to multiple classes the class-based language model as discussed herein enables generation of a more accurate probability score indicating how likely the common word follows a give sequence of one or more words in a sample text input.
摘要翻译：本公开描述了基于类的语言模型的新颖生成和使用。例如，本文中的一个实施例包括检测在单词池中不同上下文中使用的公用单词的存在，并将公共单词分配给基于类的语言模型中的多个类中的每一个。基于类的语言模型的生成和将共同词分配给多个类别，如本文所讨论的基于类的语言模型能够生成更准确的概率分数，指示通用单词遵循一个或多个单词的给出顺序的可能性一个示例文本输入。

63. 发明申请

US20140187614A1 AMINO LIPIDS, THEIR SYNTHESIS AND USES THEREOF 有权
标题翻译： AMINO脂肪，它们的合成及其用途
公开(公告)号：US20140187614A1
公开(公告)日：2014-07-03
申请号：US14124468
申请日：2012-05-15
申请人： Gary Davidson , Pavel Levkin , Linxian Li , Yi Su , David Zahner
发明人： Gary Davidson , Pavel Levkin , Linxian Li , Yi Su , David Zahner
IPC分类号： A61K9/127
CPC分类号： A61K9/1272 , C07C317/44 , C07C323/60 , C07D295/125 , C07D295/185 , Y10T428/2982
摘要： The present invention provides new amino lipids and a convenient method for synthesising these compounds. These (cationic) amino lipids have good properties as transfection agents. The method is an economic versatile two step synthesis allowing the preparation of various amino lipids thus leading to the assembly of a combinatorial library of transfection agents. Moreover, the present invention provides lipid particles (liposomes) containing said amino lipids and their use for delivering bioactive agents into cells. The invention encompasses also the use of lipid particles containing the cationic amino lipids as medicament.
摘要翻译：本发明提供新的氨基脂质和合成这些化合物的方便方法。这些（阳离子）氨基脂质作为转染剂具有良好的性质。该方法是经济通用的两步合成，允许制备各种氨基脂质，从而导致转染试剂组合文库的组装。此外，本发明提供含有所述氨基脂质的脂质颗粒（脂质体）及其将生物活性剂递送到细胞中的用途。本发明还包括使用含有阳离子氨基脂质的脂质颗粒作为药物。

64. 发明授权

US08610235B2 Trench MOSFET with integrated Schottky barrier diode 有权
标题翻译：集成肖特基势垒二极管的沟槽MOSFET
公开(公告)号：US08610235B2
公开(公告)日：2013-12-17
申请号：US13241126
申请日：2011-09-22
申请人： Daniel Calafut , Yi Su , Jongoh Kim , Hong Chang , Hamza Yilmaz , Daniel S. Ng
发明人： Daniel Calafut , Yi Su , Jongoh Kim , Hong Chang , Hamza Yilmaz , Daniel S. Ng
IPC分类号： H01L29/47
CPC分类号： H01L29/7813 , H01L21/823487 , H01L27/06 , H01L27/0629 , H01L29/0649 , H01L29/0653 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/7806 , H01L29/872
摘要： A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.
摘要翻译：肖特基二极管包括形成在半导体衬底上的半导体层; 第一和第二沟槽形成在半导体层中，其中第一和第二沟槽衬有薄介电层，并部分地填充有沟槽导体层，并且第一和第二沟槽的剩余部分填充有第一介电层; 以及形成在所述第一沟槽和所述第二沟槽之间的所述半导体层的顶表面上的肖特金属层。肖特基二极管由肖特基金属层作为阳极形成，第一和第二沟槽之间的半导体层作为阴极形成。第一和第二沟槽中的每一个中的沟槽导体层电连接到肖特基二极管的阳极。在一个实施例中，肖特基二极管与同一半导体衬底上的沟槽场效应晶体管集成。

65. 发明申请

US20130196300A1 ROBOT ASSISTED SURGICAL TRAINING 有权
标题翻译：机器人辅助手术训练
公开(公告)号：US20130196300A1
公开(公告)日：2013-08-01
申请号：US13582907
申请日：2011-03-04
申请人： Weimin Huang , Jiang Liu , Jiayin Zhou , Jing Zhang , Beng Hai Lee , Wing Kee Wong , Ngan Meng Tan , Zhou Zhang , Fengshou Yin , Stephen Chang , Chee Kong Chui , Yi Su
发明人： Weimin Huang , Jiang Liu , Jiayin Zhou , Jing Zhang , Beng Hai Lee , Wing Kee Wong , Ngan Meng Tan , Zhou Zhang , Fengshou Yin , Stephen Chang , Chee Kong Chui , Yi Su
IPC分类号： G09B23/28
CPC分类号： G09B23/28 , G06F19/00 , G09B23/30
摘要： A surgical training system and method. The system comprises means for recording reference data representing a reference manipulation of a computer generated model of an object by a master user; means for physically guiding a trainee user based on the recorded reference data during a training manipulation of the model of the object by the trainee user; and means for recording assessment data representing an assessment manipulation of the model of the object by the trainee user without guidance.
摘要翻译：外科手术训练系统及方法该系统包括用于记录表示由主用户计算机生成的对象的模型的参考操纵的参考数据的装置; 用于在由所述受训用户对所述对象的模型的训练操纵期间基于所记录的参考数据物理地引导所述受训用户的装置; 以及用于在没有指导的情况下记录代表对象的模型的评估操纵的评估数据的方法。

66. 发明申请

US20110227155A1 INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET 有权
标题翻译：将感测FET集成到分立功率MOSFET中
公开(公告)号：US20110227155A1
公开(公告)日：2011-09-22
申请号：US13149051
申请日：2011-05-31
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/8234 , H01L27/088 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/66734 , H01L29/7815 , H01L2224/0603 , H01L2924/13091 , H01L2924/00
摘要： A main FET and one or more sense FETs are formed in a common substrate. The main FET and sense FET(s) include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and sense FET(s). An electrical isolation may be between the gate terminals of the main FET and the sense FET(s). A sense pad in electrical contact with the source of the one or more sense FETs does not overlap an area of the device containing the sense FET(s). It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：主FET和一个或多个感测FET形成在公共衬底中。主FET和感测FET包括源极端子，栅极端子和漏极端子。公共栅极焊盘连接主FET和检测FET的栅极端子。电隔离可以在主FET的栅极端子和感测FET之间。与一个或多个感测FET的源极电接触的感测焊盘不与包含感测FET的器件的区域重叠。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

67. 发明申请

US20110220990A1 SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT 有权
标题翻译： SHIELDED GATE TRENCH MOS与改进的来源PICKUP布局
公开(公告)号：US20110220990A1
公开(公告)日：2011-09-15
申请号：US12722384
申请日：2010-03-11
申请人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
发明人： Hong Chang , Yi Su , Wenjun Li , Limin Weng , Gary Chen , Jongoh Kim , John Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/28
CPC分类号： H01L29/7811 , H01L21/26586 , H01L21/283 , H01L27/088 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
摘要翻译：一种制造半导体器件的方法包括使用第一掩模形成多个沟槽。沟槽包括位于终端区域外部和两个相邻有效区域之间的源拾取沟槽。使用第二掩模形成由中间介电区分隔的第一和第二导电区域。使用第三掩模形成到第一导电区域的第一电接触和到第二导电区域的第二电接触，并形成源极金属区域。使用第四掩模形成与栅极金属区域的接触。半导体器件包括位于端子区域外部并位于器件的有源区域外部的源极拾取触点。

68. 发明申请

US20110076815A1 Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection 有权
标题翻译：降低了具有静电放电（ESD）电路保护功率的MOSFET的掩模配置
公开(公告)号：US20110076815A1
公开(公告)日：2011-03-31
申请号：US12925820
申请日：2010-10-29
申请人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
发明人： Anup Bhalla , Xiaobin Wang , Wei Wang , Yi Su , Daniel Ng
IPC分类号： H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。该半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成体部注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

69. 发明申请

US20110024917A1 MULTI-DIE PACKAGE 有权
标题翻译：多模包装
公开(公告)号：US20110024917A1
公开(公告)日：2011-02-03
申请号：US12534057
申请日：2009-07-31
申请人： Anup Bhalla , Yi Su , David Grey
发明人： Anup Bhalla , Yi Su , David Grey
IPC分类号： H01L25/065 , H01L21/50
CPC分类号： H01L23/49562 , H01L23/4952 , H01L23/49575 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/0603 , H01L2224/32145 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12032 , H01L2924/13091 , H01L2924/30107 , H01L2924/00 , H01L2224/48824
摘要： A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.
摘要翻译：多管芯封装具有多个引线，第一和第二半导体管芯叠加并结合在一起，形成管芯堆叠。管芯堆叠具有相对的第一和第二面，其中第一和第二半导体管芯中的每一个具有栅极，漏极和源极区以及栅极，漏极和源极接触。第一相对侧具有与第一组多个引线电连通的第二半导体管芯的漏极接触。第一半导体管芯的栅极，漏极和源极接触以及第二半导体管芯的栅极和源极触点设置在所述相对侧的第二侧上并且与第二组多个引线电连通。用于第一半导体管芯的源极的引线可以与第二半导体管芯的漏极引线相同。

70. 发明申请

US20100320461A1 INTEGRATION OF SENSE FET INTO DISCRETE POWER MOSFET 有权
标题翻译：将感应FET集成到分立功率MOSFET中
公开(公告)号：US20100320461A1
公开(公告)日：2010-12-23
申请号：US12870489
申请日：2010-08-27
申请人： Yi Su , Anup Bhalla
发明人： Yi Su , Anup Bhalla
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7815 , H01L21/8234 , H01L27/088 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs. A transistor portion of the sense FET is surrounded by transistors of the main FET. An electrical isolation structure that surrounds the main FET is configured to electrically isolate source and body regions of the main FET from source and body regions of the sense FET. A sense FET source pad is located at an edge of the main FET and spaced apart from the transistor portion of the sense FET. The sense FET source pad is connected to the transistor portion of the sense FET by a sense FET probe metal. The isolation structure is configured such that the transistor portion of the sense FET and the sense FET source pad are located outside an active area of the main FET.
摘要翻译：半导体器件包括主场效应晶体管（FET）和一个或多个感测FET。感测FET的晶体管部分被主FET的晶体管包围。围绕主FET的电隔离结构被配置为将主FET的源极和主体区域与感测FET的源极和体区电气隔离。感测FET源极焊盘位于主FET的边缘并与感测FET的晶体管部分间隔开。感测FET源极焊盘通过感测FET探针金属连接到感测FET的晶体管部分。隔离结构被配置为使得感测FET和感测FET源极焊盘的晶体管部分位于主FET的有效区域之外。

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