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61. 发明申请

US20130002626A1 DISPLAY DEVICE 有权
标题翻译：显示设备
公开(公告)号：US20130002626A1
公开(公告)日：2013-01-03
申请号：US13583086
申请日：2011-04-07
申请人： Hajime Washio
发明人： Hajime Washio
IPC分类号： G06F3/038 , G09G3/36
CPC分类号： G09G3/2085 , G09G3/3614 , G09G3/3648 , G09G2300/0857 , G09G2330/021
摘要： An objective of the present invention is to provide a display device capable of reducing a circuit area on a panel substrate and realizing low power consumption by drive using memory.In a pixel memory portion of a display device, as corresponding to each pixel memory unit, there are provided a flip-flop (11), a voltage selection portion (12), which selects either white display voltage (VW) or black display voltage (VBL) in accordance with an output signal (Qn+1, Qn+1B) from the flip-flop (11), and a liquid crystal capacitance (13), which reflects the voltage selected by the voltage selection portion (12) in the display state of the pixel that corresponds to the flip-flop (11). Moreover, the flip-flops (11) respectively included in the pixel memory units within the pixel memory portion are connected in series, forming a shift register (110).
摘要翻译：本发明的目的是提供一种能够减少面板基板上的电路面积并通过使用存储器的驱动实现低功耗的显示装置。在显示装置的像素存储器部分中，对应于每个像素存储单元，设置有触发器（11），电压选择部分（12），其选择白色显示电压（VW）或黑色显示电压根据来自触发器（11）的输出信号（Qn + 1，Qn + 1B）和液晶电容（13）反映由电压选择部分（12）选择的电压的液晶电容对应于触发器（11）的像素的显示状态。此外，分别包括在像素存储器部分内的像素存储器单元中的触发器（11）串联连接，形成移位寄存器（110）。

62. 发明授权

US07786968B2 Pulse output circuit, driving circuit for display device and display device using the pulse output circuit, and pulse output method 失效
标题翻译：脉冲输出电路，显示装置的驱动电路和使用脉冲输出电路的显示装置，以及脉冲输出方式
公开(公告)号：US07786968B2
公开(公告)日：2010-08-31
申请号：US11002684
申请日：2004-12-03
申请人： Makoto Yokoyama , Hajime Washio , Yuhichiroh Murakami , Kenji Hyoudou , Hiroshi Murofushi
发明人： Makoto Yokoyama , Hajime Washio , Yuhichiroh Murakami , Kenji Hyoudou , Hiroshi Murofushi
IPC分类号： H03M1/50
CPC分类号： G09G3/3688 , G09G2310/0289 , G09G2310/0294
摘要： An output pulse of a flip flop is delayed in a delay inverter circuit before supplied to an input terminal of a level shifter. Then, an output pulse of the next stage flip flop is supplied to a reset terminal of the first flip flop and also to an enable terminal of the level shifter. Further, the level shifter output a sampling pulse with a beginning end equal to the beginning end of the pulse supplied to the input terminal and a terminal and equal to the beginning and of the pulse supplied to the enable terminal. With this arrangement, the subject invention provides a pulse output circuit, a driving circuit for a display device using the pulse output circuit, a display device and a pulse output method, that reduce delay of the terminal end of the pulse in sequentially outputting pulses from plural output terminals.
摘要翻译：触发器的输出脉冲在提供给电平移位器的输入端子之前在延迟逆变器电路中被延迟。然后，下一级触发器的输出脉冲被提供给第一触发器的复位端，并且还提供给电平移位器的使能端。此外，电平移位器输出采样脉冲，其开始端等于提供给输入端子的脉冲的起始端和等于提供给使能端的脉冲的开始和脉冲。通过这种布置，本发明提供了一种脉冲输出电路，一种使用脉冲输出电路的显示装置的驱动电路，一种显示装置和一种脉冲输出方法，该方法减少脉冲终端的延迟，从而顺序地从多个输出端子。

63. 发明授权

US07733321B2 Shift register and display device using same 有权
标题翻译：移位寄存器和显示设备使用相同
公开(公告)号：US07733321B2
公开(公告)日：2010-06-08
申请号：US11543219
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.
摘要翻译：移位寄存器包括多级触发器。作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

64. 发明申请

US20090115716A1 Shift register, circuit driving display device, and display device 有权
标题翻译：移位寄存器，电路驱动显示装置和显示装置
公开(公告)号：US20090115716A1
公开(公告)日：2009-05-07
申请号：US11921116
申请日：2006-06-12
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Noboru Matsuda , Hajime Washio
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Noboru Matsuda , Hajime Washio
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0232 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2340/0442 , G11C19/28
摘要： In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.
摘要翻译：在本发明的一个实施例中，本移位寄存器是设置在显示设备中的移位寄存器，通过该移位寄存器可以获得部分屏幕显示。移位寄存器包括设置在中间级中的移位停止电路，并且在部分屏幕显示中停止移位寄存器的第一级和最后级之间的移位寄存器的操作。移位寄存器还包括一个电路，其被提供在除了中间级之外的阶段中，使得该电路不执行信号处理而用作信号路径。该电路与配置中的换挡停止电路相同。上述可以改善采用本移位寄存器的显示装置的显示质量。

65. 发明申请

US20070242021A1 Level shifter circuit and display device provided therewith 有权
公开(公告)号：US20070242021A1
公开(公告)日：2007-10-18
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

66. 发明授权

US06996203B2 Bidirectional shift register and display device incorporating same 失效
标题翻译：双向移位寄存器和包含其的显示装置
公开(公告)号：US06996203B2
公开(公告)日：2006-02-07
申请号：US10860660
申请日：2004-06-04
申请人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
发明人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
IPC分类号： G11C19/00
CPC分类号： G06F5/01 , G09G3/006 , G09G3/20 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0289 , G09G2330/12
摘要： The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section for changing in waveform a signal output of one of the flip-flops which is in a first predetermined stage; and an inspection signal switching section for switching, in accordance with the direction instruct signal, an output between the signal output which has been changed in waveform in the waveform change section and a signal output of one of the flip-flops which is in a second predetermined stage.
摘要翻译：本发明包括：移位寄存器部分，包括与时钟信号同步操作的多级触发器，用于根据外部提供的方向指示信号切换移位方向; 波形变化部分，用于改变处于第一预定阶段的触发器之一的信号输出的波形; 以及检查信号切换部，根据方向指示信号，切换波形变化部中波形变化的信号输出与第二个触发器中的一个触发器的信号输出之间的输出预定阶段。

67. 发明申请

US20050175138A1 Shift register and display device 有权
标题翻译：移位寄存器和显示设备
公开(公告)号：US20050175138A1
公开(公告)日：2005-08-11
申请号：US11044003
申请日：2005-01-28
申请人： Eiji Matsuda , Yuhichiroh Murakami , Sachio Tsujino , Hajime Washio
发明人： Eiji Matsuda , Yuhichiroh Murakami , Sachio Tsujino , Hajime Washio
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C19/00 , G11C19/28 , H03K17/693
CPC分类号： G09G3/3688 , G11C19/00 , G11C19/28
摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.
摘要翻译：在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并且生成从其重叠部分被去除的输出信号A（A 1，A 2，...）。波形定时形成部输出通过提取在对应的相位差检测部中产生的输出信号A（A 1，A 2，...）的周期而获得的输出信号X（X 1，X 2，...）当来自相应触发器的输出信号Q（Q 1，Q 2，...）为高时，为高电平。输出信号X（X 1，X 2，...）在下一阶段设置触发器。根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。也可以实现具有移位寄存器的显示装置。

68. 发明授权

US09368056B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US09368056B2
公开(公告)日：2016-06-14
申请号：US13583086
申请日：2011-04-07
申请人： Hajime Washio
发明人： Hajime Washio
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/2085 , G09G3/3614 , G09G3/3648 , G09G2300/0857 , G09G2330/021
摘要： In a pixel memory portion of a display device, as corresponding to each pixel memory unit, there are provided a flip-flop, a voltage selection portion, which selects either white display voltage or black display voltage in accordance with an output signal from the flip-flop, and a liquid crystal capacitance, which reflects the voltage selected by the voltage selection portion in the display state of the pixel that corresponds to the flip-flop. Moreover, the flip-flops respectively included in the pixel memory units within the pixel memory portion are connected in series, forming a shift register.
摘要翻译：在显示装置的像素存储器部分中，对应于每个像素存储单元，设置有触发器，电压选择部分，其根据来自翻转的输出信号选择白色显示电压或黑色显示电压以及液晶电容，其在与触发器对应的像素的显示状态下反映由电压选择部选择的电压。此外，分别包括在像素存储器部分内的像素存储器单元中的触发器串联连接，形成移位寄存器。

69. 发明申请

US20120319935A1 DISPLAY DEVICE 有权
标题翻译：显示设备
公开(公告)号：US20120319935A1
公开(公告)日：2012-12-20
申请号：US13581357
申请日：2011-04-07
申请人： Hajime Washio
发明人： Hajime Washio
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G02F2001/133388 , G09G3/2085 , G09G2300/0857
摘要： An objective of the present invention is to provide a display device which operates with low power consumption and is highly flexible with respect to design of image display.Provided on a substrate which constitutes a liquid crystal panel are a normal display portion, in which image display is performed by typical active-matrix drive, and a memory display portion, in which image display is performed by memory drive. Each pixel in the memory display portion is shaped so as to include a curve or a side not parallel to either gate bus lines (GL) or source bus lines (SL). A plurality of pixel memory units (PMU), each including a flip-flop, are provided so as to correspond to their respective pixels in the memory display portion. Display data (DATA) is provided to the pixel memory unit (PMU(1)) that corresponds to the first stage of a shift register which is constituted by connecting the flip-flops in the plurality of pixel memory units (PMU) in series.
摘要翻译：本发明的目的是提供一种以低功耗工作的显示装置，并且对于图像显示器的设计而言是高度灵活的。提供在构成液晶面板的基板上的是通过典型的有源矩阵驱动执行图像显示的正常显示部分和通过存储器驱动执行图像显示的存储器显示部分。存储器显示部分中的每个像素被成形为包括与栅极总线（GL）或源极总线（SL）不平行的曲线或侧面。提供了各自包括触发器的多个像素存储单元（PMU），以便与存储器显示部分中的它们各自的像素对应。将显示数据（DATA）提供给与通过串联连接多个像素存储单元（PMU）中的触发器构成的移位寄存器的第一级对应的像素存储单元（PMU（1））。

70. 发明授权

US08248348B2 Level shifter circuit and display device provided therewith 有权
标题翻译：电平移位电路和显示装置
公开(公告)号：US08248348B2
公开(公告)日：2012-08-21
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175 , H03L5/00 , G09G5/00 , G09G3/28 , G09G3/36
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.
摘要翻译：电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。

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