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61. 发明授权

US09601614B2 Composite semiconductor device with different channel widths 有权
公开(公告)号：US09601614B2
公开(公告)日：2017-03-21
申请号：US14669415
申请日：2015-03-26
申请人： Won Gi Min , Pete Rodriquez , Hongning Yang , Jiang-Kai Zuo
发明人： Won Gi Min , Pete Rodriquez , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L27/02 , H01L29/08 , H01L29/66 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7816 , H01L27/0211 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/1095 , H01L29/66681 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.

62. 发明授权

US09117841B2 Mergeable semiconductor device with improved reliability 有权
标题翻译：合并半导体器件具有可靠性提高
公开(公告)号：US09117841B2
公开(公告)日：2015-08-25
申请号：US14047348
申请日：2013-10-07
申请人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L27/01 , H01L21/336 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L27/088 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/36 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/786 , H01L29/78615 , H01L29/78624 , H01L29/78654
摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
摘要翻译：一种器件包括半导体衬底，设置在半导体衬底中的源极和漏极区域，具有第一导电类型，并且彼此横向间隔开;以及复合体区域，设置在半导体衬底中并且具有第二导电类型。复合体区域包括沿着源极和漏极区域横向延伸的第一阱区域和设置在第一阱区域中的第二阱区域。漏极区域设置在第二阱区域中，使得载流子从第一阱区域流入第二阱区域以到达漏极区域。第二阱区域包括具有比第一阱区域更低的净掺杂剂浓度水平的第一导电类型的掺杂剂。凹槽可以设置在漏极延伸区域中并且被配置成沿着栅极结构的边缘建立耗尽区域。

63. 发明申请

US20130234246A1 Semiconductor Device with Composite Drift Region 有权
标题翻译：具有复合漂移区域的半导体器件
公开(公告)号：US20130234246A1
公开(公告)日：2013-09-12
申请号：US13413440
申请日：2012-03-06
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/76
CPC分类号： H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in the semiconductor substrate, having a second conductivity type. The composite drift region includes a first drift region and a second drift region spaced from the channel region by the first drift region. The device further includes a drain region in the semiconductor substrate, spaced from the channel region by the composite drain region, and having the second conductivity type. The first drift region has a dopant concentration profile with a first concentration level where adjacent the channel region and a second concentration level where adjacent the second drift region, the first concentration level being higher than the second concentration level. In some embodiments, the first and second drift regions are stacked vertically, with the first drift region being shallower than the second drift region.
摘要翻译：一种器件包括半导体衬底，具有第一导电类型的半导体衬底中的沟道区域和具有第二导电类型的半导体衬底中的复合漂移区域。复合漂移区域包括第一漂移区域和第一漂移区域与沟道区域间隔开的第二漂移区域。该器件还包括在半导体衬底中的漏极区域，通过复合漏极区域与沟道区域间隔开并具有第二导电类型。第一漂移区域具有第一浓度水平的掺杂剂浓度分布，其中邻近通道区域的第一浓度水平和与第二漂移区域相邻的第二浓度水平，第一浓度水平高于第二浓度水平。在一些实施例中，第一漂移区域和第二漂移区域垂直堆叠，其中第一漂移区域比第二漂移区域浅。

64. 发明授权

US08513734B2 Switch mode converter employing dual gate MOS transistor 有权
标题翻译：采用双栅极MOS晶体管的开关模式转换器
公开(公告)号：US08513734B2
公开(公告)日：2013-08-20
申请号：US13069158
申请日：2011-03-22
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/76
CPC分类号： H01L27/0705 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/41775 , H01L29/66659 , H01L29/7831 , H01L29/7835
摘要： A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.
摘要翻译：适用于可以以超过例如5MHz或更大的开关频率工作的开关模式转换器的公开的功率晶体管包括覆盖在半导体衬底的上表面上的栅极电介质层和覆盖的半导体衬底的第一和第二栅电极栅介质层。第一栅电极横向定位成覆盖在衬底的第一区域上。第一衬底区域具有第一类型的掺杂，其可以是n型或p型。功率晶体管的第二栅电极覆盖栅极电介质，并且横向地位于衬底的第二区域上方。第二衬底区域具有与第一类型不同的第二掺杂类型。晶体管还包括位于衬底内的漂移区域，该漂移区域紧邻衬底的上表面并横向地位于第一和第二衬底区域之间。

65. 发明授权

US08247869B2 LDMOS transistors with a split gate 有权
标题翻译： LDMOS晶体管与分闸
公开(公告)号：US08247869B2
公开(公告)日：2012-08-21
申请号：US12767536
申请日：2010-04-26
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/1083 , H01L29/402 , H01L29/42376 , H01L29/4238 , H01L29/456 , H01L29/66659 , H01L29/7835
摘要： A transistor including a source region, drain region, channel region, drift region, isolation region, a first gate structure over the channel region, and a second gate structure over the isolation region is provided. The drift region includes a first portion located under the isolation region and a second portion located laterally adjacent to the isolation region. The first gate structure is separated by a first separation space from the second gate structure. The first separation space is located over a portion of the second portion of the drift region and a portion of the isolation region.
摘要翻译：提供了一种晶体管，其包括源极区，漏极区，沟道区，漂移区，隔离区，沟道区上的第一栅极结构以及隔离区上的第二栅极结构。漂移区域包括位于隔离区下方的第一部分和位于横向邻近隔离区域的第二部分。第一栅极结构由第一分隔空间与第二栅极结构隔开。第一分离空间位于漂移区的第二部分的一部分和隔离区的一部分之上。

66. 发明授权

US07649234B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US07649234B2
公开(公告)日：2010-01-19
申请号：US12129861
申请日：2008-05-30
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L21/26586 , H01L21/823807 , H01L21/823892 , H01L29/1045 , H01L29/1083 , H01L29/66659
摘要： An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms a gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain.
摘要翻译：半导体器件的实施例包括覆盖衬底的栅电极和形成在衬底上的轻掺杂外延层。高能注入区域在轻掺杂外延层的源极侧形成阱。自对准的晕圈植入区域形成在器件的源极侧和高能阱植入体内。在轻掺杂外延层的漏极侧的注入区域形成栅极重叠LDD（GOLD）。卤素注入区域内的掺杂区域形成源。栅极重叠LDD（GOLD）内的掺杂区域形成漏极。

67. 发明授权

US07411270B2 Composite capacitor and method for forming the same 有权
标题翻译：复合电容器及其形成方法
公开(公告)号：US07411270B2
公开(公告)日：2008-08-12
申请号：US11397493
申请日：2006-04-03
申请人： Won Gi Min , Geno L. Fallico , Amanda M. Kroll , Hongning Yang , Jiang-Kai Zuo
发明人： Won Gi Min , Geno L. Fallico , Amanda M. Kroll , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L27/04
CPC分类号： H01G4/33 , H01G4/236 , H01L23/5223 , H01L27/0805 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78) formed over the substrate and being electrically connected to the second conductor of the capacitor.
摘要翻译：电子组件（98）包括衬底（20），具有形成在衬底上的第一和第二导体（38,54）的电容器，形成在衬底上并且电连接到第一衬底的第一组导电构件（76）电容器的导体，以及形成在衬底上并且电连接到电容器的第二导体的第二组导电构件（78）。

68. 发明申请

US20160284841A1 Composite Semiconductor Device with Different Channel Widths 有权
标题翻译：具有不同通道宽度的复合半导体器件
公开(公告)号：US20160284841A1
公开(公告)日：2016-09-29
申请号：US14669415
申请日：2015-03-26
申请人： Won Gi Min , Pete Rodriquez , Hongning Yang , Jiang-Kai Zuo
发明人： Won Gi Min , Pete Rodriquez , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7816 , H01L27/0211 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/1095 , H01L29/66681 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构在饱和区域中具有比第二多个晶体管结构中的每个晶体管结构更低的电阻。

69. 发明申请

US20160099341A1 HIGH BREAKDOWN VOLTAGE LDMOS DEVICE 有权
标题翻译：高电压LDMOS器件
公开(公告)号：US20160099341A1
公开(公告)日：2016-04-07
申请号：US14968343
申请日：2015-12-14
申请人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66
CPC分类号： H01L29/66689 , H01L21/76229 , H01L21/76264 , H01L29/0653 , H01L29/1083 , H01L29/66484 , H01L29/66772 , H01L29/7824
摘要： A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
摘要翻译：多区域（81,83）横向扩散金属氧化物半导体（LDMOS）器件（40）具有绝缘体上半导体（SOI）支撑结构（21），其上形成有基本上对称的横向内部的第一LDMOS区域（81）和基本不对称的横向边缘邻近的第二LDMOS区域（83）。深沟槽隔离（DTI）壁（60）基本上横向地终止横向边缘邻近的第二LDMOS区域（83）。通过在SOI中提供掺杂的SC掩埋层区域（86）来避免由与DTI壁（60）相关联的横向边缘邻近的第二LDMOS区域（83）表现出的电场增强和较低的源极 - 漏极击穿电压（BVDSS）靠近DTI壁（60）的支撑结构（21），位于横向边缘邻近的第二LDMOS区域（83）的一部分下方并且具有与横向边缘邻近的第二LDMOS区域的漏极区域（31）相反的导电类型 83）。

70. 发明授权

US09070576B2 Semiconductor device and related fabrication methods 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US09070576B2
公开(公告)日：2015-06-30
申请号：US13606797
申请日：2012-09-07
申请人： Hongning Yang , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/08 , H01L29/78 , H01L29/45 , H01L29/49 , H01L29/06 , H01L29/10
CPC分类号： H01L29/0878 , H01L29/0653 , H01L29/1087 , H01L29/1095 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66689 , H01L29/7824
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.
摘要翻译：提供半导体器件结构和相关的制造方法。在具有第一导电类型的半导体材料的掺杂区域上制造半导体器件的示例性方法包括在掺杂区域内形成具有第二导电类型的第一区域，形成覆盖第一区域的具有第一导电类型的体区，以及在所述掺杂区域内形成具有所述第二导电类型的漂移区，其中所述漂移区的至少一部分邻接所述第一区的至少一部分。在一个实施例中，第一区域的掺杂剂浓度小于体区的掺杂剂浓度，并且不同于漂移区的掺杂剂浓度。

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