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61. 发明申请

US20100013531A1 PHASE-LOCKED LOOP CIRCUITS AND METHODS IMPLEMENTING PULSEWIDTH MODULATION FOR FINE TUNING CONTROL OF DIGITALLY CONTROLLED OSCILLATORS 失效
标题翻译：相位锁定环路和数字控制振荡器精细调谐控制的实现脉冲调制方法
公开(公告)号：US20100013531A1
公开(公告)日：2010-01-21
申请号：US12173140
申请日：2008-07-15
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/093 , H03L7/1075 , H03L2207/50
摘要： PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.
摘要翻译：提供PLL（锁相环）电路和方法，其中PWM（脉宽调制）技术将实现DCO（数字控制振荡器）电路的连续微调控制。通常，应用脉冲宽度调制技术来进一步调制用于增强DCO的频率调谐分辨率的抖动控制信号，使得抖动控制信号被施加到DCO的分数跟踪控制端口，用于所选择的部分采用全时钟信号脉冲宽度调制。

62. 发明授权

US06903579B2 Pipelined low-voltage current-mode logic with a switching stack height of one 失效
标题翻译：流水线低电流电流模式逻辑，开关堆叠高度为1
公开(公告)号：US06903579B2
公开(公告)日：2005-06-07
申请号：US10607468
申请日：2003-06-26
申请人： Sergey V. Rylov , Alexander V. Rylyakov
发明人： Sergey V. Rylov , Alexander V. Rylyakov
IPC分类号： H03K19/173 , H03K19/20
CPC分类号： H03K19/1738
摘要： Multiple-input CML gates with a stack height of one are provided by using a composite device wherein input signals are propagated to the output through two or more stages of CML-like primitives connected in succession. A universal three-input CML gate (a 2:1 multiplexor) is provided by using a two-stage pipeline, and can be used to build other logic devices, such as AND, OR, and XOR functions, or a latch. The pipelined CML gates with a stack height of one provide a substantially improved voltage-speed trade-off under low-voltage conditions.
摘要翻译：通过使用复合器件提供堆叠高度为1的多输入CML门，其中输入信号通过连续连接的两个或多个类似CML的原语传播到输出。通过使用两级管线提供通用三输入CML门（2：1多路复用器），并可用于构建其他逻辑器件，如AND，OR和XOR函数或锁存器。堆叠高度为1的流水线CML栅极在低电压条件下提供了显着改善的电压速度折衷。

63. 发明授权

US09268890B2 Designing photonic switching systems utilizing equalized drivers 有权
标题翻译：使用均衡驱动器设计光子交换系统
公开(公告)号：US09268890B2
公开(公告)日：2016-02-23
申请号：US13619049
申请日：2012-09-14
申请人： Benjamin G. Lee , Jonathan E. Proesel , Alexander V. Rylyakov , Clint L. Schow
发明人： Benjamin G. Lee , Jonathan E. Proesel , Alexander V. Rylyakov , Clint L. Schow
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5009 , G06F2217/02 , G06F2217/08 , G06F2217/84
摘要： Designing a photonics switching system is provided. A photonic switch diode is designed to attain each performance metric in a plurality of performance metrics associated with a photonic switching system based on a weighted value corresponding to each of the plurality of performance metrics. A switch driver circuit is selected from a plurality of switch driver circuits for the photonic switching system. It is determined whether each performance metric associated with the photonic switching system meets or exceeds a threshold value corresponding to each of the plurality of performance metrics based on the designed photonic switch diode and the selected switch driver circuit. In response to determining that each performance metric associated with the photonic switching system meets or exceeds the threshold value corresponding to each of the performance metrics, the photonic switching system is designed using the designed photonic switch diode and the selected switch driver circuit.
摘要翻译：设计了一个光子切换系统。光子开关二极管被设计为基于与多个性能度量中的每一个对应的加权值来获得与光子切换系统相关联的多个性能度量中的每个性能度量。从用于光子交换系统的多个开关驱动器电路中选择开关驱动器电路。基于设计的光子开关二极管和所选择的开关驱动器电路，确定与光子切换系统相关联的每个性能度量是否满足或超过与多个性能度量中的每一个对应的阈值。响应于确定与光子交换系统相关联的每个性能度量符合或超过对应于每个性能度量的阈值，使用所设计的光子开关二极管和所选择的开关驱动器电路来设计光子交换系统。

64. 发明授权

US08901576B2 Silicon photonics wafer using standard silicon-on-insulator processes through substrate removal or transfer 有权
标题翻译：硅光子晶片使用标准的绝缘体上硅工艺，通过衬底去除或转移
公开(公告)号：US08901576B2
公开(公告)日：2014-12-02
申请号：US13353162
申请日：2012-01-18
申请人： Fuad E. Doany , Benjamin G. Lee , Alexander V. Rylyakov , Clint L. Schow , Marc A. Taubenblatt
发明人： Fuad E. Doany , Benjamin G. Lee , Alexander V. Rylyakov , Clint L. Schow , Marc A. Taubenblatt
IPC分类号： H01L33/00 , H01L29/18 , H01L21/00
CPC分类号： H01L21/76251
摘要： Processing for a silicon photonics wafer is provided. A silicon photonics wafer that includes an active silicon photonics layer, a thin buried oxide layer, and a silicon substrate is received. The thin buried oxide layer is located between the active silicon photonics layer and the silicon substrate. An electrical CMOS wafer that includes an active electrical layer is also received. The active silicon photonics layer of the silicon photonics wafer is flip chip bonded to the active electrical layer of the electrical CMOS wafer. The silicon substrate is removed exposing a backside surface of the thin buried oxide layer. A low-optical refractive index backing wafer is added to the exposed backside surface of the thin buried oxide layer. The low-optical refractive index backing wafer is a glass substrate or silicon substrate wafer. The silicon substrate wafer includes a thick oxide layer that is attached to the thin buried oxide layer.
摘要翻译：提供了硅光子晶片的处理。接收包括有源硅光子学层，薄掩埋氧化物层和硅衬底的硅光子晶片。薄的掩埋氧化物层位于有源硅光子层和硅衬底之间。还接收包括有源电层的电CMOS晶片。硅光子晶片的有源硅光子层被倒装芯片结合到电CMOS晶片的有源电层。去除暴露出薄的掩埋氧化物层的背面的硅衬底。将低光学折射率背衬晶片添加到薄的掩埋氧化物层的暴露的背面。低光学折射率背衬晶片是玻璃衬底或硅衬底晶片。硅衬底晶片包括附着到薄掩埋氧化物层的厚氧化物层。

65. 发明申请

US20140070855A1 HYBRID PHASE-LOCKED LOOP ARCHITECTURES 有权
公开(公告)号：US20140070855A1
公开(公告)日：2014-03-13
申请号：US13608277
申请日：2012-09-10
申请人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/107
CPC分类号： H03L7/1072 , H03L7/087 , H03L7/089 , H03L7/093
摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

66. 发明授权

US08665034B2 Varactor tuning control using redundant numbering 失效
标题翻译：变容二极管调谐控制采用冗余编号
公开(公告)号：US08665034B2
公开(公告)日：2014-03-04
申请号：US13245409
申请日：2011-09-26
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03B5/08
CPC分类号： H03L7/099 , H03L2207/50
摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tuning steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.
摘要翻译：公开了用于改进变容二极管电路调谐控制的技术。例如，一种装置包括用于调谐频率值的多个变容二极管。多个变容二极管包括大约sqrt（2N）变容二极管，其中N是多个调谐步骤，并且多个变容二极管的尺寸分别为1x，2x，3x，4x。。。，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。这可以称为冗余编号。

67. 发明申请

US20140050436A1 PHOTONIC MODULATOR WITH FORWARD-AND REVERSE-BIASED DIODES FOR SEPARATE TUNING AND MODULATING ELEMENTS 有权
标题翻译：具有用于单独调谐和调制元件的前向和反向偏置二极管的光电调制器
公开(公告)号：US20140050436A1
公开(公告)日：2014-02-20
申请号：US13588871
申请日：2012-08-17
申请人： Benjamin G. Lee , Jeffrey A. Kash , Alexander V. Rylyakov , Clint L. Schow
发明人： Benjamin G. Lee , Jeffrey A. Kash , Alexander V. Rylyakov , Clint L. Schow
IPC分类号： G02F1/025 , G02F1/015
CPC分类号： G02F1/0121 , G02F1/025 , G02F1/2257
摘要： A method and structure for a modulator which includes a forward-biased diode optimized for power and area to perform a tuning function, and a reverse-biased diode optimized for speed to perform a modulation function.
摘要翻译：一种用于调制器的方法和结构，其包括针对功率和面积优化的正向偏置二极管以执行调谐功能，以及针对速度进行优化的反向偏置二极管以执行调制功能。

68. 发明申请

US20140029949A1 OPTICAL DE-MULTIPLEXING DEVICE 有权
标题翻译：光学多路复用器件
公开(公告)号：US20140029949A1
公开(公告)日：2014-01-30
申请号：US13556603
申请日：2012-07-24
申请人： Solomon Assefa , Douglas M. Gill , Jonathan E. Proesel , Alexander V. Rylyakov , Clint L. Schow
发明人： Solomon Assefa , Douglas M. Gill , Jonathan E. Proesel , Alexander V. Rylyakov , Clint L. Schow
IPC分类号： H04J14/02
CPC分类号： G02B6/12019 , H04B10/676 , H04B10/691 , H04B10/697 , H04B10/6972 , H04B17/20 , H04J14/02
摘要： An electro-optical device includes an optical de-multiplexing portion operative to output a first optical signal having a first wavelength and a second optical signal having a second wavelength, an array of photodetectors, and a switching logic portion communicatively connected to the array of photodetectors, the switching logic portion operative to determine which photodetector of the array of photodetectors is converting the first optical signal into a first electrical signal and output the first electrical signal from a first output node associated with the first optical signal.
摘要翻译：电光装置包括光解除复用部分，其操作以输出具有第一波长的第一光信号和具有第二波长的第二光信号，光电检测器阵列和通信地连接到光电检测器阵列的开关逻辑部分所述开关逻辑部分用于确定所述光电检测器阵列的哪个光电检测器将所述第一光信号转换为第一电信号，并从与所述第一光信号相关联的第一输出节点输出所述第一电信号。

69. 发明授权

US08593226B2 Transimpedance amplifier 有权
标题翻译：互阻放大器
公开(公告)号：US08593226B2
公开(公告)日：2013-11-26
申请号：US13226650
申请日：2011-09-07
申请人： Jonathan E. Proesel , Alexander V. Rylyakov , Clint L. Schow , Jose A. Tierno
发明人： Jonathan E. Proesel , Alexander V. Rylyakov , Clint L. Schow , Jose A. Tierno
IPC分类号： H03F3/08
CPC分类号： H03F3/08
摘要： A circuit includes a transimpedance amplifier portion having a first input node and a second input node, and a feedback circuit portion comprising a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal.
摘要翻译：一种电路包括具有第一输入节点和第二输入节点的跨阻放大器部分，以及反馈电路部分，包括具有连接到第一输入节点的漏极端子，源极端子和栅极端子的第一晶体管，第二晶体管具有连接到第二输入节点的漏极端子，源极端子和栅极端子，以及具有连接到第一晶体管的源极端子和第二端子的源极端子的漏极端子的第三晶体管。

70. 发明授权

US08222936B2 Phase and frequency detector with output proportional to frequency difference 有权
标题翻译：相位和频率检测器，输出与频率差成比例
公开(公告)号：US08222936B2
公开(公告)日：2012-07-17
申请号：US12813828
申请日：2010-06-11
申请人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
发明人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/1077 , H03L7/1976
摘要： Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.
摘要翻译：公开了相位和频率检测器和技术。例如，装置包括用于接收第一和第二时钟信号的第一电路，以及用于产生指示第一和第二时钟信号之间的相位差的至少一个信号。该装置还包括第二电路，用于接收由第一电路产生的至少一个信号，并响应于该至少一个接收信号，产生至少一个输出信号，其中与该至少一个输出信号相关的频率为与第一和第二时钟信号之间的频率差成比例。

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