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61. 发明授权

US06297660B2 Test carrier with variable force applying mechanism for testing semiconductor components 失效
公开(公告)号：US06297660B2
公开(公告)日：2001-10-02
申请号：US09734514
申请日：2000-12-12
申请人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
发明人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
IPC分类号： G01R3126
CPC分类号： G01R1/0466
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for testing components using the carrier, are provided. The carrier includes a base, an interconnect for making temporary electrical connections with the component, and a force applying mechanism for biasing the component against the interconnect. The force applying mechanism includes an elastomeric biasing member adapted to apply a relatively large biasing force during assembly of the carrier and a smaller biasing force in the assembled carrier. The force applying mechanism also includes a pressure plate which can include a cushioning layer with a non-stick surface for contacting the component. In addition, the cushioning layer, and elastomeric biasing member can be made of conductive elastomers to provide an electrical path from a backside of the component.

62. 发明授权

US06204678B1 Direct connect interconnect for testing semiconductor dice and wafers 有权
标题翻译：直接连接互连，用于测试半导体晶片和晶圆
公开(公告)号：US06204678B1
公开(公告)日：2001-03-20
申请号：US09302833
申请日：1999-04-30
申请人： Salman Akram , James M. Wark , Warren M. Farnworth
发明人： Salman Akram , James M. Wark , Warren M. Farnworth
IPC分类号： G01R173
CPC分类号： G01R31/2886 , G01R1/0408
摘要： An interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having patterns of contact members for electrically contacting the dice. The interconnect also includes patterns of conductors for providing electrical paths to the contact members. In addition, the interconnect includes contact receiving cavities configured to retain electrical connectors of a testing apparatus in electrical communication with the conductors. A die level test system includes the interconnect mounted to a temporary package for a singulated die. In the die level test system, the interconnect provides direct electrical access from testing circuitry to the die. A wafer level test system includes the interconnect mounted to a probe card fixture of a wafer probe handler. In the wafer level test system, the contact receiving cavities can be configured to support and align the interconnect to the probe card fixture.
摘要翻译：提供了用于测试半导体晶片的互连和系统，以及使用该互连的测试方法。互连包括具有用于电接触骰子的接触构件图案的衬底。互连还包括用于向接触构件提供电路径的导体图案。此外，互连件包括被配置为保持与导体电连通的测试装置的电连接器的接触接收腔。芯片级测试系统包括安装到用于单个模具的临时封装的互连。在芯片级测试系统中，互连提供从测试电路到芯片的直接电接入。晶片级测试系统包括安装到晶片探测器处理器的探针卡夹具上的互连。在晶片级测试系统中，触点接收腔可以被配置为支撑并将互连对准到探针卡固定装置。

63. 发明授权

US06025730A Direct connect interconnect for testing semiconductor dice and wafers 失效
标题翻译：直接连接互连，用于测试半导体晶片和晶圆
公开(公告)号：US06025730A
公开(公告)日：2000-02-15
申请号：US818456
申请日：1997-03-17
申请人： Salman Akram , James M. Wark , Warren M. Farnworth
发明人： Salman Akram , James M. Wark , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R31/28 , G01R1/73
CPC分类号： G01R31/2886 , G01R1/0408
摘要： An interconnect and system for testing semiconductor dice, and a test method using the interconnect are provided. The interconnect includes a substrate having patterns of contact members for electrically contacting the dice. The interconnect also includes patterns of conductors for providing electrical paths to the contact members. In addition, the interconnect includes contact receiving cavities configured to retain electrical connectors of a testing apparatus in electrical communication with the conductors. A die level test system includes the interconnect mounted to a temporary package for a singulated die. In the die level test system, the interconnect provides direct electrical access from testing circuitry to the die. A wafer level test system includes the interconnect mounted to a probe card fixture of a wafer probe handler. In the wafer level test system, the contact receiving cavities can be configured to support and align the interconnect to the probe card fixture.
摘要翻译：提供了用于测试半导体晶片的互连和系统，以及使用该互连的测试方法。互连包括具有用于电接触骰子的接触构件图案的衬底。互连还包括用于向接触构件提供电路径的导体图案。此外，互连件包括被配置为保持与导体电连通的测试装置的电连接器的接触接收腔。芯片级测试系统包括安装到用于单个模具的临时封装的互连。在芯片级测试系统中，互连提供从测试电路到芯片的直接电接入。晶片级测试系统包括安装到晶片探测器处理器的探针卡夹具上的互连。在晶片级测试系统中，触点接收腔可以被配置为支撑并将互连对准到探针卡固定装置。

64. 发明授权

US07452743B2 Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level 有权
标题翻译：微电子成像单元和在晶片级制造微电子成像单元的方法
公开(公告)号：US07452743B2
公开(公告)日：2008-11-18
申请号：US11217877
申请日：2005-09-01
申请人： Steven D. Oliver , Lu Velicky , William Mark Hiatt , David R. Hembree , Mark E. Tuttle , Sidney B. Rigg , James M. Wark , Warren M. Farnworth , Kyle K. Kirby
发明人： Steven D. Oliver , Lu Velicky , William Mark Hiatt , David R. Hembree , Mark E. Tuttle , Sidney B. Rigg , James M. Wark , Warren M. Farnworth , Kyle K. Kirby
IPC分类号： H01L21/00
CPC分类号： H01L21/00 , H01L21/76898 , H01L23/552 , H01L27/14609 , H01L27/14618 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies including integrated circuits, external contacts electrically coupled to the integrated circuits, and image sensors operably coupled to the integrated circuits. The individual image sensors include at least one dark current pixel at a perimeter portion of the image sensor. The method includes depositing a cover layer onto the workpiece and over the image sensors. The method further includes patterning and selectively developing the cover layer to form discrete volumes of cover layer material over corresponding image sensors. The discrete volumes of cover layer material have sidewalls aligned with an inboard edge of the individual dark current pixels such that the dark current pixels are not covered by the discrete volumes.
摘要翻译：本文公开了用于在晶片级制造多个成像单元的微电子成像单元和方法。在一个实施例中，制造多个成像单元的方法包括提供具有多个成像管芯的成像工件，所述成像管芯包括集成电路，电耦合到集成电路的外部触点以及可操作地耦合到集成电路的图像传感器。各个图像传感器包括在图像传感器的周边部分处的至少一个暗电流像素。该方法包括将覆盖层沉积在工件上并在图像传感器上方。该方法还包括图案化和选择性地显影覆盖层以在对应的图像传感器上形成分离体积的覆盖层材料。覆盖层材料的离散体积具有与各个暗电流像素的内侧边缘对准的侧壁，使得暗电流像素不被离散体积覆盖。

65. 发明授权

US6078186A Force applying probe card and test system for semiconductor wafers 失效
公开(公告)号：US6078186A
公开(公告)日：2000-06-20
申请号：US1409
申请日：1997-12-31
申请人： David R. Hembree , Warren M. Farnworth , James M. Wark
发明人： David R. Hembree , Warren M. Farnworth , James M. Wark
IPC分类号： G01R31/28 , G01R31/02
CPC分类号： G01R31/2886
摘要： A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; an interconnect slidably mounted to the substrate; and a force applying mechanism for biasing contacts on the interconnect into electrical engagement with contacts on the wafer. The force applying mechanism includes spring loaded electrical connectors that provide electrical paths to the interconnect, and generate a biasing force. The biasing force is controlled by selecting a spring constant of the electrical connectors, and an amount of Z-direction overdrive between the probe card and wafer. The probe card also includes a leveling mechanism for leveling the interconnect with respect to the wafer.

66. 发明授权

US06600334B1 Force applying probe card and test system for semiconductor wafers 有权
标题翻译：对半导体晶圆施加探针卡和测试系统
公开(公告)号：US06600334B1
公开(公告)日：2003-07-29
申请号：US09596272
申请日：2000-06-16
申请人： David R. Hembree , Warren M. Farnworth , James M. Wark
发明人： David R. Hembree , Warren M. Farnworth , James M. Wark
IPC分类号： G01R3126
CPC分类号： G01R31/2886
摘要： A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; an interconnect slidably mounted to the substrate; and a force applying mechanism for biasing contacts on the interconnect into electrical engagement with contacts on the wafer. The force applying mechanism includes spring loaded electrical connectors that provide electrical paths to the interconnect, and generate a biasing force. The biasing force is controlled by selecting a spring constant of the electrical connectors, and an amount of Z-direction overdrive between the probe card and wafer. The probe card also includes a leveling mechanism for leveling the interconnect with respect to the wafer.
摘要翻译：提供了用于测试半导体晶片的探针卡，测试方法和采用探针卡的测试系统。探针卡包括：基底; 可滑动地安装到基板的互连; 以及用于将互连上的触点偏置成与晶片上的触点电接合的施力机构。施力机构包括弹簧加载的电连接器，其提供到互连的电路径，并产生偏置力。通过选择电连接器的弹簧常数和探针卡和晶片之间的Z方向过驱动量来控制偏置力。探针卡还包括用于使互连相对于晶片调平的调平机构。

67. 发明授权

US06730526B2 Multi-chip module system and method of fabrication 失效
标题翻译：多芯片模块系统及其制造方法
公开(公告)号：US06730526B2
公开(公告)日：2004-05-04
申请号：US10033234
申请日：2001-12-28
申请人： Salman Akram , David R. Hembree , James M. Wark
发明人： Salman Akram , David R. Hembree , James M. Wark
IPC分类号： H01L2100
CPC分类号： H01L23/5382 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.
摘要翻译：多芯片模块系统及其制造方法，其中将多芯片模块（MCM）的故障芯片的等同物添加到先前用适当的电连接构造的空位中的模块中。各种不同的骰子可以通过适配器连接到MCM的相同空位，其中每个适配器具有相同的占位面积，但是不同的适配器能够容纳不同数量和类型的骰子。

68. 发明授权

US07166915B2 Multi-chip module system 有权
标题翻译：多芯片模块系统
公开(公告)号：US07166915B2
公开(公告)日：2007-01-23
申请号：US10032734
申请日：2001-12-28
申请人： Salman Akram , David R. Hembree , James M. Wark
发明人： Salman Akram , David R. Hembree , James M. Wark
IPC分类号： H01L23/34
CPC分类号： H01L23/5382 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.
摘要翻译：多芯片模块系统及其制造方法，其中将多芯片模块（MCM）的故障芯片的等同物添加到先前用适当的电连接构造的空位中的模块中。各种不同的骰子可以通过适配器连接到MCM的相同空位，其中每个适配器具有相同的占位面积，但是不同的适配器能够容纳不同数量和类型的骰子。

69. 发明授权

US06720652B2 Apparatus providing redundancy for fabricating highly reliable memory modules 失效
标题翻译：提供用于制造高度可靠的存储器模块的冗余的装置
公开(公告)号：US06720652B2
公开(公告)日：2004-04-13
申请号：US10213185
申请日：2002-08-05
申请人： Salman Akram , James M. Wark , David R. Hembree
发明人： Salman Akram , James M. Wark , David R. Hembree
IPC分类号： H01L2334
CPC分类号： H01L23/5382 , H01L24/97 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/14 , H05K1/0292 , H05K1/0295 , H05K2201/0979 , H05K2201/10159 , H05K2201/10674 , H01L2924/00014 , H01L2924/00
摘要： A method and apparatus for repair of a multi-chip module, such as a memory module, is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.
摘要翻译：提供了一种用于修复诸如存储器模块的多芯片模块的方法和装置，其中在多芯片模块的基板上提供至少一个冗余或辅助芯片连接位置。辅助芯片安装位置优选地提供用于连接多于一种类型的替换半导体芯片的触点。因此，当发现多芯片模块上的一个或多个芯片完全或部分缺陷时，可以选择至少一个替换芯片并附加到辅助位置，以提供额外的存储器以使模块回到其设计能力。

70. 发明授权

US06531772B2 Electronic system including memory module with redundant memory capability 有权
标题翻译：电子系统包括具有冗余存储能力的存储器模块
公开(公告)号：US06531772B2
公开(公告)日：2003-03-11
申请号：US09832053
申请日：2001-04-10
申请人： Salman Akram , James M. Wark , David R. Hembree
发明人： Salman Akram , James M. Wark , David R. Hembree
IPC分类号： H01L2334
CPC分类号： H01L23/5382 , H01L24/97 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/14 , H05K1/0292 , H05K1/0295 , H05K2201/0979 , H05K2201/10159 , H05K2201/10674 , H01L2924/00014 , H01L2924/00
摘要： A method and apparatus for repair of a multi-chip module, such as a memory module, is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.
摘要翻译：提供了一种用于修复诸如存储器模块的多芯片模块的方法和装置，其中在多芯片模块的基板上提供至少一个冗余或辅助芯片连接位置。辅助芯片安装位置优选地提供用于连接多于一种类型的替换半导体芯片的触点。因此，当发现多芯片模块上的一个或多个芯片完全或部分缺陷时，可以选择至少一个替换芯片并附加到辅助位置，以提供额外的存储器以使模块回到其设计能力。

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